Switch for bus optimization

• US 20050154804A1
• Filed: 01/07/2005
• Published: 07/14/2005
• Est. Priority Date: 01/08/2004
• Status: Active Grant

• Current Assignee: Topside Research LLC
• Original Assignee: Topside Research LLC
• Inventors: Wong, Ken, Haywood, Chris, Stewart, Heath, Rappoport, Adam, Shaikli, Nadim, Reiner, Thomas, Vuong, Bao, De La Garrigue, Michael
• Granted Patent: US 7,426,602 B2
• Time in Patent Office: Days
• US Class Current: 710/36
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Claims

1. A method comprising:

receiving from a first device a data unit in a first port unit of a plurality of port units, the data unit destined for a second device

providing the data unit to a control matrix

evaluating in the control matrix when to send the data unit to a second port unit associated with the second device

sending the data unit from the control matrix to the second port unit

providing the data unit to the second device

2. The method of claim 1 wherein the port units do not include output logic.

3. The method of claim 1 wherein the port units do not include an output buffer.

4. The method of claim 1 wherein the evaluating is based on a PCI Express specification.

5. The method of claim 1 wherein the first device and the second device are each selected from the group comprising:

a graphics card, a sound card, a network communications unit, a computer peripheral, a computer chip set, and a processor.

6. A switch comprising:

a plurality of port units, each port unit including an ingress portion and an egress portion, the ingress portion comprising an input buffer, an input queue and input logic, and the egress portion comprising an output pipe

a control matrix coupled between the plurality of port units to prioritize and allocate bus communications between the plurality of port units.

7. The switch of claim 6 wherein the control matrix includes buffers and logic traditionally included in the egress portion of the port units.

8. The switch of claim 6 wherein the control matrix performs prioritization and allocation pursuant to a PCI Express specification.

9. The switch of claim 6 wherein the input queue includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue.

10. The switch of claim 6 implemented on a single filed programmable gate array.

11. The switch of claim 6 wherein at least two of the port units are coupled with a device.

12. The switch of claim 11 wherein the device includes one or more selected from the group comprising:

a graphics card, a sound card, a network communications unit, a computer peripheral, a computer chip set, and a processor.