Multi-processor system receiving input from a pre-fetch buffer

• US 20050154836A1
• Filed: 01/13/2004
• Published: 07/14/2005
• Est. Priority Date: 01/13/2004
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Co. (HP Inc.)
• Inventors: Steely, Simon C. Jr., Tierney, Gregory Edward
• Granted Patent: US 8,281,079 B2
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/507 using speculative control
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.

Claims

1. A multi-processor system, comprising:

a pre-fetch buffer that retrieves data as an uncached fill, such that the cache coherency state of the data remains unaltered; and

a source processor that processes the data from the pre-fetch buffer in response to a source request.

2. The system of claim 1, the source processor processing the data as a speculative data fill until a coherent signal is received, the coherent signal indicating whether the speculative data fill is coherent.

3. The system of claim 2, the source processor continuing to execute program instructions with the speculative data fill.

4. The system of claim 3, the source processor having a request engine that sends a source request to obtain at least one data fill from the multi-processor system.

5. The system of claim 4, the at least one data fill comprising a coherent data fill, and the source processor returning to a previous state and processing the coherent data fill if it is indicated that the speculative data fill is not a coherent copy of the data.

6. The system of claim 5, further comprising a fill control component that compares the coherent data fill with the speculative data fill, the fill control component providing the coherent data fill to the source processor if the speculative data fill is the same as coherent data fill and providing the coherent signal to the source processor if the speculative data fill is the not the same as the coherent data fill.

7. The system of claim 4, the coherent signal indicating a coherent data fill from the at least one data fill.

8. The system of claim 4, the request engine generating a miss address file (MAF) entry associated with the source request, the MAF having a field for storing the at least one data fill and a coherent flag that indicates if the coherent signal has been received by the source processor.

9. The system of claim 8, the request engine storing a latest data fill received by the source processor in the MAF entry field for storing at least one data fill and changing the state of the coherent flag in response to receipt of the coherent signal by the source processor.

10. A multi-processor system comprising:

a pre-fetch buffer that stores uncached data fills associated with a pre-fetch request;

a source processor that receives an uncached data fill from the pre-fetch buffer in response to a source request and executes with the uncached data fill; and

the system employing a cache coherency protocol that returns a coherent copy of the data fill and a coherent signal in response to the source request.

11. The system of claim 10, the source processor executing with the uncached data fill while the coherent copy of the data fill is being obtained.

12. The system of claim 11, the system further comprising a fill control that compares the uncached data fill provided by the pre-fetch buffer to the coherent copy of the data fill, the source processor returning to its state prior to executing the uncached fill if the uncached data fill does not match the coherent copy.

13. A multi-processor system comprising:

means for executing program instructions associated with a source processor;

means for retrieving a data fill, having an associated state, from at least one other processor without changing the associated state of the data fill;

means for storing the retrieved data fill at a buffer to be provided to the means for executing; and

means for providing a coherent signal that indicates if the retrieved data fill is coherent at the time it is provided to the means for executing.

14. The system of claim 13, further comprising means for changing the state of the data fill once the data fill is provided to the means for executing.

15. The system of claim 13, the means for providing a coherent signal comprising means for obtaining a coherent copy of the data fill and means for comparing the coherent copy of the data fill to the retrieved data fill.

16. The system of claim 13, further comprising means for restoring the means for executing to a state of execution associated with a first time.

17. A method comprising:

storing a copy of a data fill in a pre-fetch buffer;

providing the copy of the data fill to a processor associated with the pre-fetch buffer in response to a source request; and

determining if the copy of the data fill is coherent.

18. The method of claim 17, the coherent data fill having an associated state with regard to a plurality of processors, and the data fill being uncached, such that it is stored in the pre-fetch buffer without changing the associated state of the data.

19. The method of claim 17, further comprising requesting a coherent data fill when the copied data fill is provided to the processor.

20. The method of claim 19, wherein determining if the copied data is coherent comprises comparing the copied data fill to the requested coherent data fill.

21. The method of claim 19, comprising executing program instructions with the copied data fill while the coherent data fill is being obtained.

22. The method of claim 21, further comprising restoring the processor to a previous state of execution if the copied data fill is determined not to be coherent.