Memory device and method of operation of a memory device

• US 20050154853A1
• Filed: 01/06/2005
• Published: 07/14/2005
• Est. Priority Date: 03/10/1998
• Status: Abandoned Application

• Current Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Original Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G., Bystrom, Todd W., May, Bradley A.
• Application Number:
  US11/030,231
• Publication Number:
  US 20050154853A1
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of operation of a memory device and a memory device having registers to store values representing a number of clock cycles to access and output data is provided in embodiments. Data is sensed from an array of memory cells using a plurality of sense amplifiers. A column address that identifies data sensed is latched using the plurality of sense amplifiers. The data is accessed, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address. The first number of clock cycles is represented by a first value stored in a first register on the memory device. The data is output after a second number of clock cycles have elapsed after accessing the data from the array of memory cells. The second number of clock cycles is represented by a second value stored in a second register on the memory device. A column decoder driving a column select line based on the column address accesses the data.

Claims

1-24. -24. (canceled)

25. A method of operation of a memory device having an array of memory cells, the method comprising:

sensing data from the array using a plurality of sense amplifiers;

latching a column address that identifies data sensed using the plurality of sense amplifiers;

accessing the data, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address, wherein the first number of clock cycles is represented by a first value stored in a first register on the memory device; and

outputting the data after a second number of clock cycles have elapsed after accessing the data, wherein the second number of clock cycles is represented by a second value stored in a second register on the memory device.

26. The method of claim 25, wherein accessing the data includes a column decoder driving a column select line based on the column address.

27. The method of claim 26, wherein latching a column address includes latching the column address using the column decoder.

28. The method of claim 25, further including receiving a row command, wherein sensing data from the array is performed in response to the row command.

29. The method of claim 25, further including receiving a column command, wherein latching the column address is performed in response to the column command.

30. The method of claim 29, wherein the column command specifies a read operation.

31. The method of claim 25, further including:

receiving the first value and the second value during an initialization sequence;

storing the first value in the first register; and

storing the second value in the second register.

32. The method of claim 25, wherein the first value is determined by dividing a time period of a first timing parameter of the memory device by a period of the clock signal.

33. The method of claim 25, further including synchronizing outputting the data to the clock signal using a delay lock loop circuit.

34. The method of claim 25, further including conducting initialization operations at a first frequency of operation;

and

performing memory access operations at a second frequency of operation, wherein the second frequency is higher than the first frequency.

35. A method of operation of a memory device having an array of memory cells, the method comprising:

sensing data from a row of the array of memory cells using sense amplifiers;

accessing data from the sense amplifiers, identified based on a column address, after a first number of clock cycles of a clock signal have elapsed after receiving the column address, wherein the first number of clock cycles is represented by a first value stored in a first register on the memory device;

outputting the data after a second number of clock cycles have elapsed after accessing the data from the sense amplifiers, wherein the second number of clock cycles is represented by a second value stored in a second register on the memory device; and

synchronizing outputting the data to the clock signal using a delay lock loop circuit.

36. The method of claim 35, further including activating a wordline of the row of the array of memory cells to sense the data.

37. The method of claim 35, further including latching the column address in a column decoder after receiving the column address.

38. The method of claim 37, further including receiving a column command, wherein latching the column address is performed in response to the column command.

39. The method of claim 38, wherein the column command specifies a read operation.

40. The method of claim 35, wherein accessing the data includes a column decoder driving a column select line based on the column address.

41. The method of claim 35, further including receiving a row address, wherein the row address identifies the row of the array of memory cells.

42. The method of claim 35, further including:

receiving the first value and the second value during an initialization sequence;

storing the first value in the first register; and

storing the second value in the second register.

43. The method of claim 35, wherein the first value is determined by dividing a time period of a timing parameter of the memory device by a period of the clock signal.

44. The method of claim 35, further including conducting initialization operations at a first frequency of operation;

and

performing memory access operations at a second frequency of operation, wherein the second frequency is higher than the first frequency.

45. A memory device comprising:

an array of memory cells;

a first register to store a first value;

a second register to store a second value;

sense amplifiers to sense data from a row of the array of memory cells, wherein data is accessed from the sense amplifiers, identified based on the column address, after a first number of clock cycles of a clock signal have elapsed after receiving the column address, wherein the first number of clock cycles is represented by the first value; and

an output driver to output the data after a second number of clock cycles of the clock signal have elapsed after accessing the data from the sense amplifiers, wherein the second number of clock cycles is represented by the second value.

46. The memory device of claim 45, further including a column decoder to receive the column address.

47. The memory device of claim 46, further including an interface to receive a column command, wherein the column decoder latches the column address in response to the column command.

48. The memory device of claim 47, wherein the column command specifies a read operation.

49. The memory device of claim 45, wherein the first value and the second value are received by the interface during an initialization sequence.

50. The memory device of claim 45, wherein the first value is determined by dividing a time period of a timing parameter of the memory device by a period of the clock signal.

51. The memory device of claim 45, further including a delay lock loop circuit, coupled to the output driver, to synchronize the output of the data with the clock signal.

52. The memory device of claim 51, further including a third register to store a third value, wherein the third value represents of a period of time to elapse before the memory device is ready to receive a column command when recovering from a power down mode, wherein the delay lock loop circuit reacquires synchronization with the clock signal during the period of time.

53. A memory device comprising:

an array of memory cells;

a first register to store a first value;

a second register to store a second value;

a third register to store a third value;

sense amplifiers to sense data from a row of the array of memory cells, wherein data is accessed from the sense amplifiers, identified based on the column address, after a first number of clock cycles of a clock signal have elapsed after receiving the column address, wherein the first number of clock cycles is represented by the first value; and

an output driver to output the data after a second number of clock cycles of the clock signal have elapsed after accessing the data from the sense amplifiers, wherein the second number of clock cycles is represented by the second value;

a delay lock loop circuit, coupled to the output driver, to provide synchronization of the output of the data with the clock signal, wherein synchronization is acquired during a period of time to elapse before the memory device is ready to receive a column command when recovering from a power down mode, wherein the period of time is represented by the third value.

54. The memory device of claim 53, further including:

a column decoder to receive the column address; and

an interface to receive a column command, wherein the column decoder latches the column address in response to the column command.