Examination apparatus for biological sample and chemical sample

• US 20050156207A1
• Filed: 09/03/2004
• Published: 07/21/2005
• Est. Priority Date: 01/21/2004
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Watanabe, Kazuki, Kamahori, Masao, Yazawa, Yoshiaki, Kunimoto, Yukinori
• Application Number:
  US10/933,339
• Publication Number:
  US 20050156207A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10K 30/671 Organic radiation-sensitive molecular electronic devices

Abstract

A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a pMOS transistor is formed and a p type semiconductor layer on which an nMOS transistor is formed are isolated by a pn junction. Therefore, the p type semiconductor layer at the outermost portion (chip edge portion to be in contact with solution) is set to floating, and the maximum potential and the minimum potential of the chip are supplied to an n type semiconductor layer and a p type semiconductor layer inside the outermost portion, respectively. Also, the chip is covered with an ion impermeable insulating film for reducing the penetration of positive ions through the oxide layer.

Claims

1. A semiconductor integrated circuit device formed on an SOI substrate, comprising:

a first semiconductor region of second conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of first conductivity type are formed;

a second semiconductor region of first conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of second conductivity type are formed;

a plurality of wirings formed on said first and second semiconductor regions; and

an oxide layer for electrically isolating said wirings or said wirings from said SOI substrate,

wherein sidewalls of said oxide layer are covered with an ion impermeable insulating film.

2. The semiconductor integrated circuit device according to claim 1,

wherein a first potential is supplied to said first semiconductor region and a second potential is supplied to said second semiconductor region, thereby applying reverse bias to a pn junction between said first semiconductor region and said second semiconductor region, and

said first potential is one of maximum potential and minimum potential of said semiconductor integrated circuit device and said second potential is the other of maximum potential and minimum potential of said semiconductor integrated circuit device.

3. The semiconductor integrated circuit device according to claim 2, further comprising:

a third semiconductor region of second conductivity type which is formed so as to reach a buried insulating layer of said SOI substrate and surround said integrated circuit; and

a fourth semiconductor region of first conductivity type formed on an outer periphery of said third semiconductor region,

wherein said second potential is supplied to said third semiconductor region and said fourth semiconductor region is set to floating.

4. The semiconductor integrated circuit device according to claim 1,

wherein said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,

said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and

thickness of said first and second field insulating films is smaller than that from a main surface of said SOI substrate to a buried insulating layer.

5. The semiconductor integrated circuit device according to claim 1,

wherein said ion impermeable insulating film covers also an outer periphery of a buried insulating layer of said SOI substrate.

6. The semiconductor integrated circuit device according to claim 5,

wherein said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,

said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and

said first field insulating film and said second field insulating film reach the buried insulating layer of said SOI substrate.

7. The semiconductor integrated circuit device according to claim 1,

wherein metal wirings and through hole patterns for preventing penetration and diffusion of ions from outer periphery of said oxide layer are provided.

8. The semiconductor integrated circuit device according to claim 1,

wherein an ion sensitive field effect transistor is provided.

9. The semiconductor integrated circuit device according to claim 1,

wherein a phosphosilicate glass layer or a silicon nitride layer is used as said ion impermeable insulating film.

10. A sensor chip, comprising:

a sensor portion;

a signal processing circuit for processing sensing signals from said sensor portion;

a communication control circuit for controlling a communication with an external device;

an interface circuit for converting said sensing signals processed in said signal processing circuit into radio frequency signals; and

a coil and a resonant capacitor for transmitting said radio frequency signals to said external device,

wherein said sensor portion, said signal processing circuit, said communication control circuit, said interface circuit, and said coil and resonant capacitor are integrated on a chip,

said sensor chip is formed on an SOI substrate,

a plurality of wirings formed on said SOI substrate and an oxide layer for electrically isolating said wirings or said wirings from said SOI substrate are formed, and

sidewalls of said oxide layer are covered with an ion impermeable insulating film.

11. The sensor chip according to claim 10, further comprising:

a first semiconductor region of second conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of first conductivity type are formed; and

a second semiconductor region of first conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of second conductivity type are formed,

wherein a first potential is supplied to said first semiconductor region and a second potential is supplied to said second semiconductor region, thereby applying reverse bias to a pn junction between said first semiconductor region and said second semiconductor region, and

said first potential is one of maximum potential and minimum potential of said sensor chip and said second potential is the other of maximum potential and minimum potential of said sensor chip.

12. The sensor chip according to claim 11, further comprising:

a third semiconductor region of second conductivity type which is formed so as to reach a buried insulating layer of said SOI substrate and surround said integrated circuit; and

a fourth semiconductor region of first conductivity type formed on an outer periphery of said third semiconductor region,

wherein said second potential is supplied to said third semiconductor region and said fourth semiconductor region is set to floating.

13. The sensor chip according to claim 11,

wherein said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,

said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and

thickness of said first and second field insulating films is smaller than that from a main surface of said SOI substrate to a buried insulating layer.

14. The sensor chip according to claim 11,

wherein said ion impermeable insulating film covers also an outer periphery of a buried insulating layer of said SOI substrate.

15. The sensor chip according to claim 10,

wherein said sensor chip is used in contact with a sample solution in an unpackaged state,

16. A measurement system, comprising:

reaction vessels;

a reader/writer;

an antenna connected to said reader/writer; and

sensor chips put into said reaction vessels,

wherein said sensor chip can receive signals from said antenna or transmit sensing data to said reader/writer via said antenna,

said sensor chip is formed on an SOI substrate,

a plurality of wirings formed on said SOI substrate and an oxide layer for electrically isolating said wirings are formed, and

sidewalls of said oxide layer are covered with an ion impermeable insulating film.

17. The measurement system according to claim 16,

wherein said sensor chip is used in contact with a sample solution in an unpackaged state.

18. The measurement system according to claim 16,

wherein said sensor chip includes:

a first semiconductor region of second conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of first conductivity type are formed; and

a second semiconductor region of first conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of second conductivity type are formed,

a first potential is supplied to said first semiconductor region and a second potential is supplied to said second semiconductor region, thereby applying reverse bias to a pn junction between said first semiconductor region and said second semiconductor region, and

said first potential is one of maximum potential and minimum potential of said sensor chip and said second potential is the other of maximum potential and minimum potential of said sensor chip.

19. The measurement system according to claim 18,

wherein power of said sensor chip is supplied by inductive coupling of said antenna and a coil of said sensor chip.

20. The measurement system according to claim 18,

wherein said sensor chip includes:

a third semiconductor region of second conductivity type which is formed so as to reach a buried insulating layer of said SOI substrate and surround said integrated circuit; and

a fourth semiconductor region of first conductivity type formed on an outer periphery of said third semiconductor region, and

said second potential is supplied to said third semiconductor region and said fourth semiconductor region is set to floating.

21. The measurement system according to claim 18,

wherein said sensor chip is characterized in that said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,

said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and

thickness of said first and second field insulating films is smaller than that from a main surface of said SOI substrate to a buried insulating layer.

22. The measurement system according to claim 18,

wherein said ion impermeable insulating film covers also an outer periphery of a buried insulating layer of said SOI substrate.