Circuits for transistor testing

• US 20050156605A1
• Filed: 12/23/2004
• Published: 07/21/2005
• Est. Priority Date: 12/24/2003
• Status: Active Grant

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Lee, Sang Gi
• Granted Patent: US 7,145,356 B2
• Time in Patent Office: Days
• US Class Current: 324/537
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a circuit for transistor testing, by which electrical stresses of separate conditions can be simultaneously applied to a plurality of transistors, respectively. According to one example, such a circuit may include a plurality of contact pads connectable to a plurality of terminals of a plurality of transistors, a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively, and a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively.

Claims

1. A circuit for transistor testing, comprising:

a plurality of contact pads connectable to a plurality of terminals of a plurality of transistors;

a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively; and

a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively.

2. A circuit as defined by claim 1, wherein the plurality of contact pads includes a gate pulse pad and a gate bulk pad for applying a maximum voltage to be applied to the gate of each of the transistors.

3. A circuit as defined by claim 1, wherein voltage differences between the voltages applied to the gates of a plurality of the transistors are equal to each other.

4. A circuit as defined by claim 1, wherein voltage differences between the voltages applied to the drains of a plurality of the transistors are equal to each other.

5. An integrated circuit, which includes a plurality of transistors and a test circuit for measuring degradation degrees of a plurality of the transistors, the test circuit comprising:

a plurality of contact pads connectable to a plurality of terminals of a plurality of the transistors;

a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively; and

a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively.

6. A circuit as defined by claim 5, wherein a plurality of the contact pads include a gate pulse pad and a gate bulk pad for applying a maximum voltage to be applied to the gate of each of the transistors.

7. A circuit as defined by claim 5, wherein voltage differences between the voltages applied to the gates of a plurality of the transistors are equal to each other.

8. A circuit as defined by claim 5, wherein voltage differences between the voltages applied to the drains of a plurality of the transistors are equal to each other.