Non-quasistatic rectifier circuit

• US 20050156656A1
• Filed: 09/21/2004
• Published: 07/21/2005
• Est. Priority Date: 01/15/2004
• Status: Abandoned Application

• Current Assignee: Tap Development LLC (Intellectual Ventures LLC)
• Original Assignee: Tap Development LLC (Intellectual Ventures LLC)
• Inventors: Rotzoll, Robert R., Dimmler, Klaus
• Application Number:
  US10/945,775
• Publication Number:
  US 20050156656A1
• Time in Patent Office: Days
• US Class Current: 327/423
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A non-quasistatic MOS rectifier circuit uses a bridge-rectifier configuration using four organic PMOS transistors, an antenna coil to induce a differential input signal, and an output capacitor for filtering the rectified output signal. The VSS or ground-connected transistors are diode-connected with the gate connection on the coil side of the transistor channel. The VDD-connected transistors have gates connected to the opposing VDD-connected transistor source that is connected to the coil. This configuration results in full-wave rectification. The gates are all connected to the coil and thereby become part of the capacitance of the radio frequency parallel resonant network. The transistor gates are then switched at the rate of the radio frequency signal with no delay relative to the coil voltage. Operation of the organic transistors is based on non-quasistatic behavior of the transistor. Non-quasistatic operation results in rectification at a frequency much higher than the quasistatic limit of transistor unity gain bandwidth.

Claims

1. A rectifier circuit comprising a plurality of organic MOS transistors operating in a non-quasistatic mode of operation.

2. The rectifier circuit of claim 1 further comprising an antenna coil for providing a differential input signal.

3. The rectifier circuit of claim 1 further comprising a capacitor to provide sufficient additional capacitance beyond the gate capacitance of the MOS transistors to resonate the paralled tuned network to a predetermined frequency.

4. The rectifier circuit of claim 1 further comprising a load capacitor for filtering a rectified output signal.

5. The rectifier circuit of claim 1 comprising:

first and second input terminals for receiving a differential input signal;

an output terminal for providing a rectified output signal;

a first diode-connected PMOS transistor coupled between the first input terminal and ground;

a second diode-connected PMOS transistor coupled between the second input terminal and ground;

a third PMOS transistor having a drain coupled to the output terminal, a gate coupled to the second input terminal, and a source coupled to the first input terminal; and

a fourth PMOS transistor having a drain coupled to the output terminal, a gate coupled to the first input terminal, and a source coupled to the second input terminal.

6. The rectifier circuit of claim 1 comprising:

first and second input terminals for receiving a differential input signal;

an output terminal for providing a rectified output signal;

a first diode-connected NMOS transistor coupled between the output terminal and the first input terminal;

a second diode-connected NMOS transistor coupled between the output terminal and the second input terminal;

a third NMOS transistor having a drain coupled to ground, a gate coupled to the second input terminal, and a source coupled to the first input terminal; and

a fourth NMOS transistor having a drain coupled to ground, a gate coupled to the first input terminal, and a source coupled to the second input terminal.

7. The rectifier circuit of claim 1 comprising:

first and second input terminals for receiving a differential input signal;

an output terminal for providing a rectified output signal;

a first NMOS transistor having a drain coupled to ground, a gate coupled to the second input terminal, and a source coupled to the first input terminal; and

a second NMOS transistor having a drain coupled to ground, a gate coupled to the first input terminal, and a source coupled to the second input terminal.

a first PMOS transistor having a drain coupled to the output terminal, a gate coupled to the second input terminal, and a source coupled to the first input terminal; and

a second PMOS transistor having a drain coupled to the output terminal, a gate coupled to the first input terminal, and a source coupled to the second input terminal.

8. The rectifier circuit of claim 1 wherein the large-signal input frequency of an input differential signal exceeds 1 MHz.

9. The rectifier circuit of claim 1 wherein the organic MOS transistor comprises an organic polymer field-effect transistor.

10. The rectifier circuit of claim 1 wherein the organic MOS transistors each comprise a semiconducting polymer films.

11. The rectifier circuit of claim 10 wherein the semiconducting polymer film comprises pentacene, hexithiphene, TPD, or PBD.

12. The rectifier circuit of claim 10 wherein the semiconducting polymer film comprises polythiophene, parathenylene vinylene, and polyphenylene ethylene, or polyvinyl carbazole.

13. The rectifier circuit of claim 1 in which the organic MOS transistors are operated at alternating current frequencies in excess of the unity gain bandwidth of the transistor.

14. A method of rectifying an input signal comprising operating a plurality of organic MOS transistors in a non-quasistatic mode of operation to iteratively supply a current pulse to a load capacitor.

15. The method of claim 14 wherein the method comprises operating a plurality of PMOS transistors.

16. The method of claim 14 wherein the method comprises operating a plurality of NMOS transistors.

17. The method of claim 14 wherein the frequency exceeds 1 MHz.

18. The method of claim 14 wherein the organic MOS transistors are operated at alternating current frequencies in excess of the unity gain bandwidth of the transistor.

19. A rectifier circuit comprising:

first and second input terminals for receiving a differential input signal;

an output terminal for providing a rectified output signal;

a first diode-connected organic PMOS transistor coupled between the first input terminal and ground;

a second diode-connected organic PMOS transistor coupled between the second input terminal and ground;

a third organic PMOS transistor having a drain coupled to the output terminal, a gate coupled to the second input terminal, and a source coupled to the first input terminal;

a fourth organic PMOS transistor having a drain coupled to the output terminal, a gate coupled to the first input terminal, and a source coupled to the second input terminal;

an antenna coil coupled between the first and second input terminals for providing the differential input signal; and

a load capacitor coupled between the output terminal and ground for filtering the rectified output signal.

20. The rectifier circuit of claim 19 in which each of the transistors comprises a transistor operating in a non-quasistatic mode of operation.