Periodic patterns and technique to control misalignment between two layers

• US 20050157297A1
• Filed: 02/18/2005
• Published: 07/21/2005
• Est. Priority Date: 04/10/2001
• Status: Abandoned Application

• Current Assignee: Ibrahim Abdulhalim, Michael Faeyrman, Michael Friedmann, Mike Adel
• Original Assignee: Ibrahim Abdulhalim, Michael Faeyrman, Michael Friedmann, Mike Adel
• Inventors: Friedmann, Michael, Abdulhalim, Ibrahim, Adel, Mike, Faeyrman, Michael
• Application Number:
  US11/062,255
• Publication Number:
  US 20050157297A1
• Time in Patent Office: Days
• US Class Current: 356/401
• CPC Class Codes: G01B 11/14 for measuring distance or clearance between spaced objects or spaced apertures G01B11/26 takes precedence; rangefinders G01C3/00
• CPC Class Codes: G01B 11/26 for measuring angles or tapers; for testing the alignment of axes
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method and system to measure misalignment error between two overlying or interlaced periodic structures are proposed. The overlying or interlaced periodic structures are illuminated by incident radiation, and the diffracted radiation of the incident radiation by the overlying or interlaced periodic structures are detected to provide an output signal. The misalignment between the overlying or interlaced periodic structures may then be determined from the output signal.

Claims

1-54. -54. (canceled)

55. A method of measuring line profile asymmetries in microelectronic devices, the method comprising the steps of:

directing light at an array of microelectronic features of a microelectronic device;

detecting light scattered back from the array comprising one or more features at one or more wavelengths; and

comparing one or more characteristics of the back-scattered light by performing a model comparison.

56. The method of claim 55 wherein the directing step comprises directing light at substantially a single wavelength.

57. The method of claim 55 wherein the directing step comprises directing light at a plurality of wavelengths.

58. The method of claim 55, wherein the comparing step comprises comparing light intensity.

59. The method of claim 55, wherein the comparing step additionally comprises comparing phase.

60. The method of claim 55, wherein the comparing step additionally comprises comparing ratios of light magnitude and light phase.

61. The method of claim 55, wherein the directing and detecting steps are performed by a spectral scatterometer.

62. The method of claim 55, wherein the detecting step comprises decomposing back-scattered light into S and P components relative to a plane of incidence.

63. The method of claim 55, wherein the detecting step comprises detecting specular order diffracted light.

64. The method of claim 55, additionally comprising the step of employing the results of the comparing step to detect asymmetries selected from the group consisting of asymmetries within a single layer of the microelectronic device and asymmetries within multiple layers of the microelectronic device.

65. The method of claim 64, additionally comprising the step of controlling a manufacturing process if results of the comparing step indicate an asymmetry in the array.

66. An apparatus for measuring line-profile asymmetries in microelectronic devices, said apparatus comprising:

means for directing light at an array of microelectronic features of a microelectronic device;

means for detecting light scattered back from the array comprising one or more features at one or more wavelengths; and

means for comparing one or more characteristics of the back-scattered light by performing a model comparison.

67. The apparatus of claim 66 wherein said directing means comprises means for directing light at substantially a single wavelength.

68. The apparatus of claim 66 wherein said directing means comprises means for directing light at a plurality of wavelengths.

69. The apparatus of claim 66 wherein said comparing means additionally comprises means for comparing light intensity.

70. The apparatus of claim 66 wherein said comparing means additionally comprises means for comparing phase.

71. The apparatus of claim 66 wherein said comparing means additionally comprises means for comparing ratios of light magnitude and light phase.

72. The apparatus of claim 66 wherein said directing and detecting means comprise a spectral scatterometer.

73. The apparatus of claim 66 wherein said detecting means comprises means for decomposing back-scattered light into S and P components relative to a plane of incidence.

74. The apparatus of claim 66 wherein said detecting means comprises means for detecting specular order diffracted light.

75. The apparatus of claim 66, additionally comprising means for employing the results of the comparing step to detect asymmetries selected from the group consisting of asymmetries within a single layer of the microelectronic device and asymmetries within multiple layers of the microelectronic device.

76. The apparatus of claim 75 additionally comprising means for controlling a manufacturing process if said comparing means indicates an asymmetry in the array.