Integrated memory device with multi-sector selection commands

• US 20050157553A1
• Filed: 11/08/2004
• Published: 07/21/2005
• Est. Priority Date: 11/06/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Schillaci, Paolino, Mazzara, Salvatore, Perroni, Maurizio Francesco
• Granted Patent: US 7,457,908 B2
• Time in Patent Office: Days
• US Class Current: 365/185.110
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An integrated memory device is proposed. The memory device includes a flash memory having an address parallelism and a data parallelism; the flash memory is partitioned into a plurality of blocks each one including a plurality of sectors, which can be erased individually. A Low Pin Count communication interface is used to receive a command from an external bus, which has a transfer parallelism lower than the address parallelism and the data parallelism; the command includes a selection field for selecting each sector of one or more blocks individually. A control unit then executes an operation corresponding to the command in respect of each selected sector.

Claims

1. An integrated memory device including:

a flash memory having an address parallelism and a data parallelism, the flash memory being partitioned into a plurality of blocks each one including a plurality of sectors being erasable individually,

a communication interface for receiving a command from an external bus having a transfer parallelism lower than the address parallelism and the data parallelism, the command including a selection field for selecting each sector of at least one block individually, and

control means for executing an operation corresponding to the command in respect of each selected sector.

2. The integrated memory device according to claim 1, wherein the at least one selected block consists of a single block, the selection field including an address of the selected block and a selection mask for the sectors of the selected block.

3. The integrated memory device according to claim 2, wherein the operation is an erase operation of each selected sector.

4. The integrated memory device according to claim 3, wherein the command includes a main code identifying the erase operation and a secondary code having a first value, a second value or a third value, when the secondary code has the first value the selection field selecting each sector of a block individually and the control means erasing each selected sector, when the secondary code has the second value the selection field selecting a single block and the control means erasing all the sectors of the selected block, and when the secondary code has the third value the selection field selecting a single sector and the control means erasing the selected sector.

5. The integrated memory device according to claim 4, wherein the erase command requires a first and a second communication cycles with the external bus each one involving the transmission of a command field, an address field and a data field, in the first communication cycle the command field including the main code and the data field including the secondary code, and in the second communication cycle when the secondary code has the first value the address field including the address of the selected block and the data field including the selection mask, when the secondary field has the second value the address field including the address of the selected block, and when the secondary field has the third value the address field including the address of the selected sector.

6. The integrated memory device according to claim 5, further including means for storing an erase mask, means for applying an erase pulse to each sector of the selected block according to the erase mask, means for generating a further selection mask of all the sectors of the selected block in response to the secondary code having the second value or a still further selection mask of the selected sector in response to the secondary code having the third value, and means for setting the erase mask according to the selection mask in response to the secondary code having the first value, to the further selection mask in response to the secondary code having the second value, and to the still further selection mask in response to the secondary code having the third value.

7. The integrated memory device according to claim 2, wherein a protection register is associated with each sector, the operation being a write operation of the protection register of each selected sector.

8. The integrated memory device according to claim 7, further including means for switching the integrated memory device between a first operative mode and a second operative mode, and means for switching the integrated memory device between a first configuration and a second configuration, in the first operative mode the selection field selecting each sector of a block individually and the control means writing the protection register of each selected sector, in the second operative mode with the first configuration the selection field selecting a single block and the control means writing the protection registers of all the sectors of the selected block, and in the second operative mode with the second configuration the selection field selecting a single sector and the control means writing the protection register of the selected sector.

9. The integrated memory device according to claim 8, wherein the write command requires at least one communication cycle with the external bus involving the transmission of a command field, an address field and a data field, wherein in the first operative condition the write command requires a first and a second communication cycles, in the first communication cycle the command field including a write code identifying the write operation and the data field including a value to be written on the protection register of each selected sector, and in the second communication cycle the address field including the address of the selected block and the data field including the selection mask, and wherein in the second operative condition the write command requires a single communication cycle, the command field including the write code, the address field including the address of the selected block and further including the address of the selected sector with the second configuration, and the data field including the value to be written on the protection register of each selected sector.

10. The integrated memory device according to claim 9, further including means for enabling the update of each protection register according to a write mask, means responsive to the write code for generating a further selection mask of all the sectors of the selected block in the second operative mode with the first configuration or a still further selection mask of the selected sector in the second operative mode with the second configuration, and means for setting the write mask according to the selection mask in the first operative mode, to the further selection mask in the second operative mode with the first configuration, and to the still further selection mask in the second operative mode with the second configuration.

11. An integrated memory device including:

a flash memory having an address parallelism and a data parallelism, the flash memory being partitioned into a plurality of blocks each one including a plurality of sectors being erasable individually,

a Low Pin Count communication interface for receiving a command from an external bus having a transfer parallelism lower than the address parallelism and the data parallelism, the command including a selection field for selecting each sector of at least one block individually, and

a control unit for executing an operation corresponding to the command in respect of each selected sector.

12. A data processing system including an integrated memory device, at least one external unit, and an external bus for connecting the integrated memory device with the at least one external unit, wherein the integrated memory device includes:

a flash memory having an address parallelism and a data parallelism, the flash memory being partitioned into a plurality of blocks each one including a plurality of sectors being erasable individually,

a communication interface for receiving a command from the external bus, the external bus having a transfer parallelism lower than the address parallelism and the data parallelism, wherein the command includes a selection field for selecting each sector of at least one block individually, and

control means for executing an operation corresponding to the command in respect of each selected sector.

13. A computer including an integrated memory device, a microprocessor, and a local bus for connecting the integrated memory device with the microprocessor, wherein the integrated memory device includes:

a flash memory having an address parallelism and a data parallelism, the flash memory being partitioned into a plurality of blocks each one including a plurality of sectors being erasable individually,

a Low Pin Count communication interface for receiving a command from the local bus, the local bus having a transfer parallelism lower than the address parallelism and the data parallelism, wherein the command includes a selection field for selecting each sector of at least one block individually, and

a control unit for executing an operation corresponding to the command in respect of each selected sector.

14. A method of operating an integrated memory device including a flash memory having an address parallelism and a data parallelism, the flash memory being partitioned into a plurality of blocks each one including a plurality of sectors being erasable individually, wherein the method includes the steps of:

receiving a command from an external bus having a transfer parallelism lower than the address parallelism and the data parallelism, the command including a selection field for selecting each sector of at least one block individually, and

executing an operation corresponding to the command in respect of each selected sector.

15. The method according to claim 14, wherein the at least one selected block consists of a single block, the selection field including an address of the selected block and a selection mask for the sectors of the selected block.

16. The method according to claim 15, wherein the operation is an erase operation of each selected sector.

17. The method according to claim 16, wherein the command includes a main code identifying the erase operation and a secondary code having a first value, a second value or a third value, when the secondary code has the first value the selection field selecting each sector of a block individually and the step of executing the operation including erasing each selected sector, when the secondary code has the second value the selection field selecting a single block and the step of executing the operation including erasing all the sectors of the selected block, and when the secondary code has the third value the selection field selecting a single sector and the step of executing the operation including erasing the selected sector.

18. The method according to claim 17, wherein the erase command requires a first and a second communication cycles with the external bus each one involving the transmission of a command field, an address field and a data field, in the first communication cycle the command field including the main code and the data field including the secondary code, and in the second communication cycle when the secondary code has the first value the address field including the address of the selected block and the data field including the selection mask, when the secondary field has the second value the address field including the address of the selected block, and when the secondary field has the third value the address field including the address of the selected sector.

19. The method according to claim 18, further including the steps of:

generating a further selection mask of all the sectors of the selected block in response to the secondary code having the second value or a still further selection mask of the selected sector in response to the secondary code having the third value,

setting an erase mask according to the selection mask in response to the secondary code having the first value, to the further selection mask in response to the secondary code having the second value, and to the still further selection mask in response to the secondary code having the third value, and

applying an erase pulse to each sector of the selected block according to the erase mask.

20. The method according to claim 15, wherein a protection register is associated with each sector, the operation being a write operation of the protection register of each selected sector.

21. The method according to claim 20, further including the step of:

switching the integrated memory device between a first operative mode and a second operative mode, and

switching the integrated memory device between a first configuration and a second configuration,

in the first operative mode the selection field selecting each sector of a block individually and the step of executing the operation including writing the protection register of each selected sector, in the second operative mode with the first configuration the selection field selecting a single block and the step of executing the operation including writing the protection registers of all the sectors of the selected block, and in the second operative mode with the second configuration the selection field selecting a single sector and the step of executing the operation including writing the protection register of the selected sector.

22. The method according to claim 21, wherein the write command requires at least one communication cycle with the external bus involving the transmission of a command field, an address field and a data field, wherein in the first operative condition the write command requires a first and a second communication cycles, in the first communication cycle the command field including a write code identifying the write operation and the data field including a value to be written on each selected sector, and in the second communication cycle the address field including the address of the selected block and the data field including the selection mask, and wherein in the second operative condition the write command requires a single communication cycle, the command field including the write code, the address field including the address of the selected block and further including the address of the selected sector with the second configuration, and the data field including the value to be written on each selected sector.

23. The method according to claim 22, further including the steps of:

in response to the write code, generating a further selection mask of all the sectors of the selected block in the second operative mode with the first configuration or a still further selection mask of the selected sector in the second operative mode with the second configuration,

setting a write mask according to the selection mask in the first operative mode, to the further selection mask in the second operative mode with the first configuration, and to the still further selection mask in the second operative mode with the second configuration, and

enabling the update of each protection register according to a write mask.

24. A memory device including a plurality of memory blocks, each block including a plurality of sectors that are individually accessible and the memory device being adapted to receive a command that includes selection data for the sectors of at least one memory block, and the memory device operable in response to the command to perform an operation on the sectors corresponding to the selection data.

25. The memory device of claim 24 wherein the operation performed in response to the command comprises an erase operation.

26. The memory device of claim 24 wherein the selection data comprises a selection mask for the sectors of each memory block, the selection mask identifying specific sectors to be erased within each block.

27. The memory device of claim 24 wherein the selection data portion of the command is received during a single communications cycle.

28. A method of operating a memory device including a bus and including a plurality of memory blocks, each memory block including a plurality of sectors being individually accessible, the method comprising:

receiving a command on the bus, the command including selection data associated with the sectors of at least one memory block; and

accessing the sectors in each memory block responsive to the selection data.

29. The method of claim 28 wherein accessing sectors in each memory block comprises erasing the sectors in each memory block that correspond to the associated selection data.

30. The method of claim 28 wherein the selection data includes an address for each memory block and for each such memory block includes a selection mask for the sectors of the block.

31. The method of claim 28 wherein receiving a command on the bus occurs during first and a second communication cycles.