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Memory device supporting a dynamically configurable core organization

  • US 20050157579A1
  • Filed: 03/12/2005
  • Published: 07/21/2005
  • Est. Priority Date: 06/26/2002
  • Status: Abandoned Application
First Claim
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1. A dynamically configurable memory comprising:

  • a. configuration logic having a configuration-logic input terminal adapted to receive data indicative of a first or second memory core configuration and a configuration-logic output terminal providing configuration signals corresponding to the first and second memory core configurations; and

    b. a dynamic memory core having;

    i. a plurality of physical memory banks, each bank having associated therewith at least one device data line; and

    ii. a core control circuit including a memory-core control terminal connected to the configuration-logic output terminal and memory-core data terminals connected to respective ones of the device data lines;

    c. wherein the first memory core configuration divides the memory core into a first collection of logical memory banks, each logical memory bank including a first number of the physical memory banks, where the first number is at least one; and

    d. wherein the second memory core configuration divides the memory core into a second collection of logical memory banks, each logical memory bank including a second number of the physical memory banks, where the second number is greater than the first number.

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