Multi-queue single-FIFO architecture for quality of service oriented systems
First Claim
1. A multi-queue network apparatus for quality of service oriented communication, comprising:
- a host system comprising a system memory and a peripheral bus, the system memory including a plurality of queues each of which is configured to store data packets to be transmitted; and
a peripheral module comprising;
an arbiter, adapted to interface with the peripheral bus, maintaining a plurality of next access pointers targeting each queue within the system memory, respectively, determining which queue is to be serviced next contingent upon a quality of service policy, and fetching at least one data packet identified by the chosen queue'"'"'s next access pointer;
a FIFO buffer, connected to the arbiter, storing and managing the fetched data packet in a first-in-first-out manner; and
physical layer interface logic, connected to the FIFO buffer, accepting therefrom each data packet, if available, and preparing the data packet for transmission on a physical medium.
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Accused Products
Abstract
A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue'"'"'s next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.
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Citations
10 Claims
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1. A multi-queue network apparatus for quality of service oriented communication, comprising:
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a host system comprising a system memory and a peripheral bus, the system memory including a plurality of queues each of which is configured to store data packets to be transmitted; and
a peripheral module comprising;
an arbiter, adapted to interface with the peripheral bus, maintaining a plurality of next access pointers targeting each queue within the system memory, respectively, determining which queue is to be serviced next contingent upon a quality of service policy, and fetching at least one data packet identified by the chosen queue'"'"'s next access pointer;
a FIFO buffer, connected to the arbiter, storing and managing the fetched data packet in a first-in-first-out manner; and
physical layer interface logic, connected to the FIFO buffer, accepting therefrom each data packet, if available, and preparing the data packet for transmission on a physical medium. - View Dependent Claims (2, 3)
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4. A multi-queue network apparatus for quality of service oriented communication, comprising:
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a host system comprising a system memory and a peripheral bus, the system memory including a plurality of queues each of which is configured to store data packets to be transmitted; and
a peripheral module comprising;
an arbiter, adapted to interface with the peripheral bus, maintaining a plurality of next access pointers targeting each queue within the system memory, respectively, determining which queue is to be serviced next contingent upon a quality of service policy, and fetching at least one data packet identified by the chosen queue'"'"'s next access pointer;
a data path controller, connected to the arbiter, accepting therefrom the fetched data packet; and
two FIFO buffers, connected in parallel to the data path controller, storing and managing the fetched data packet in a first-in-first-out manner;
wherein the data path controller allows one of the FIFO buffers to be filled with the fetched data packet while the other FIFO buffer is engaged in outgoing transference. - View Dependent Claims (5, 6, 7)
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8. An apparatus for servicing multiple queues in a host system using reduced number of FIFO buffers, comprising:
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an arbiter for maintaining a plurality of next access pointers for the multiple queues storing data packets to be transmitted, determining which queue is to be serviced next contingent upon a quality of service policy, and fetching at least one data packet, which is identified by the chosen queue'"'"'s next access pointer, through a peripheral bus by means of direct memory access;
a FIFO buffer, connected to the arbiter, storing and managing the fetched data packet in a first-in-first-out manner; and
physical layer interface logic, connected to the FIFO buffer, accepting therefrom each data packet, if available, and preparing the data packet for transmission on a physical medium. - View Dependent Claims (9, 10)
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Specification