Yield based, in-line defect sampling method

• US 20050158887A1
• Filed: 02/09/2005
• Published: 07/21/2005
• Est. Priority Date: 08/21/1998
• Status: Abandoned Application

• Current Assignee: Steven J. Simmons
• Original Assignee: Steven J. Simmons
• Inventors: Simmons, Steven J.
• Application Number:
  US11/054,266
• Publication Number:
  US 20050158887A1
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (ICs). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations. The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Claims

1. A wafer comprising:

a plurality of semiconductor dice located on a wafer having a determined number of defects, each of the defects having a known size and location and having an effect of semiconductor die yield for the plurality of semiconductor dice of the wafer, an estimated semiconductor die yield loss (DYL) of the semiconductor die of the plurality of semiconductor dice of the wafer determined based on number and weight of the defect(s) on each semiconductor die of the plurality of semiconductor dice of the wafer, the estimated semiconductor die yield loss having lower and upper limits for summing all of the DYL of the plurality of semiconductor dice on the wafer for obtaining a wafer yield loss (WYL), the defects of the plurality of semiconductor dice of the wafer subdivided into a plurality of size range populations of defects for the plurality of semiconductor dice of the wafer, the relative contribution of each size range population of defects of the plurality of the semiconductor dice determining the wafer yield loss (WYL).

2. The wafer of claim 1, wherein the DYL comprises calculating an estimated die yield loss having lower and upper limits of zero and 1.0, respectively.

3. The wafer of claim 2, wherein the lower limit comprises a representation of no yield loss attributable to the defects and the upper limit comprises a representation of fatal yield loss attributable to the defects.

4. The wafer of claim 1, wherein subdividing the defects into the plurality of size range populations of defects comprises subdividing the defects into a plurality of 0 to 10 size range populations.

5. An in-process wafer comprising:

a plurality of semiconductor dice on a wafer having defects classified by size and location for classifying each of the defects into one of size range populations of defects in a computer file, each defect having a weight assigned thereto for representing an estimated effect of the defects on die yield for the semiconductor dice, an estimated die yield loss (DYL) for each semiconductor die of the semiconductor dice determined based on number and weight of the defects on each semiconductor die of the plurality of semiconductor dice, all DYL of the plurality of semiconductor dice on the wafer summed for obtaining a wafer yield loss (WYL), the defects of the plurality of semiconductor dice of the wafer subdivided into a plurality of size range populations of defects for determining a relative contribution of each size range population of defects of the plurality to the WYL, the relative contribution of each size range population of defects of the plurality of defects to the wafer yield loss is determined by discarding data for each size range population of defects of the plurality and calculating, in turn, a drop in the WYL for combined size range populations excepting the discarded data, summing the calculated WYL to obtain a drop sum, dividing the drop sum to determine a relative drop attributable to each size range population of defects of the plurality, and randomly selecting defects from each size range population of defects of the plurality.

6. The in-process wafer of claim 5, further comprising:

randomly selecting defects from each size range population of defects of the plurality, a number selected from each size range population of defects of the plurality in proportion to the relative contribution thereof, the randomly selected defects being weighted to represent defects having a greatest effect on yield losses.

7. The in-process wafer of claim 6, further comprising:

reviewing the randomly selected defects and determining in-line action required to reduce wafer yield losses.

8. The in-process wafer of claim 7, wherein reviewing the randomly selected defects includes visual inspection by a microscope.

9. The in-process wafer of claim 7, wherein determining in-line action comprises determining if an individual semiconductor die of the semiconductor dice on the wafer is acceptable to proceed in a manufacturing process.

10. The in-process wafer of claim 5, wherein determining defects on the semiconductor dice is performed by an automated surface inspection tool.

11. A plurality of semiconductor dice in wafer form comprising:

a plurality of semiconductor dice having defects classified by size and location by assigning a weight to each of the defects representing an estimated effect of each defect on die yield, an estimated die yield loss (DYL) for each of the plurality of semiconductor dice determined based on number and weight of the defects on each of the plurality of semiconductor dice in wafer form for summing all DYL of the plurality of semiconductor dice on a wafer to obtain a wafer yield loss (WYL), the defects subdivided into a plurality of size range populations of defects, a relative contribution determined of each size range population of defects of the plurality to the WYL, defects randomly selected from each size range population of defects of the plurality, a number selected from each size range population of defects of the plurality in proportion to the relative contribution thereof, the randomly selected defects weighted to represent defects having a greatest effect on yield losses.

12. The plurality of semiconductor dice in wafer form of claim 11, further comprising:

defects being randomly selected by reviewing the defects for determining in-line action required to reduce the WYL.

13. The plurality of semiconductor dice in wafer form of claim 11, wherein each of the defects being classified into one of the plurality of size range populations of defects.

14. The plurality of semiconductor dice in wafer form of claim 11, wherein the estimated die yield loss calculated has lower and upper limits of zero and 1.0, respectively.

15. The plurality of semiconductor dice in wafer form of claim 14, wherein the lower limit comprises a representation of no yield loss attributable to the defects and the upper limit comprises a representation of fatal yield loss attributable to the defects.

16. The plurality of semiconductor dice in wafer form of claim 11, wherein the defects are subdivided into a plurality of 0 to 10 size range populations.

17. The plurality of semiconductor dice in wafer form of claim 11, wherein the relative contribution of each size range population of defects of the plurality to the WYL being determined by discarding data for each size range population of defects of the plurality and calculating, in turn, a drop in WYL for combined size range populations excepting the discarded data, summing the calculated drop in WYL to obtain a drop sum, and dividing the drop sum to determine a relative drop attributable to each size range population of defects of the plurality.

18. The plurality of semiconductor dice in wafer form of claim 12, wherein the in-line action required to reduce the WYL determining if an individual semiconductor die of the plurality of semiconductor dice in wafer form is acceptable to proceed in a manufacturing process.