Methods of forming thin-film transistor display devices

• US 20050158926A1
• Filed: 02/24/2005
• Published: 07/21/2005
• Est. Priority Date: 02/29/1996
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-gyu
• Granted Patent: US 7,259,035 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

Methods of forming thin-film transistor display devices including forming a gate line and a gate electrode on a face of a substrate and forming a semiconductor layer that is insulated from the gate line. A data line and a source/drain electrode are formed on the semiconductor layer. The data line and the source/drain electrode are formed as composites of at least two different metal conductive layers. A transparent pixel electrode is formed that is electrically coupled to the drain electrode.

Claims

1. A method of forming a thin-film transistor display device, comprising the steps of:

forming a gate line and a gate electrode on a face of a substrate;

forming a semiconductor layer insulated from the gate electrode, opposite the face;

forming a data line and a source/drain electrode on the semiconductor layer, the data line and the source/drain electrode comprising a composite of at least two layers, in which the composite comprises at least two metals of a different element therein;

forming a pixel electrode electrically coupled to the drain electrode;

forming a first conductive pattern electrically connected to an end portion of the gate line; and

forming a second conductive pattern electrically connected to an end portion of the data line.

2. The method of claim 1, wherein the pixel electrode, the first conductive pattern and the second conductive pattern are made of the same material.

3. The method of claim 1, wherein the step of forming a gate electrode comprises a step of forming the gate electrode comprising a composite of at least two layers, in which the composite comprises at least two metals of a different element therein.

4. The method of claim 1, wherein the step of forming the semiconductor layer insulated from the gate electrode comprises the steps of:

forming a gate electrode insulating layer on the gate electrode; and

forming the semiconductor layer on the gate electrode insulating layer.

5. The method of claim 4, wherein the step of forming the semiconductor layer comprises the steps of:

forming a first amorphous silicon layer on the gate electrode insulating layer; and

forming a second amorphous silicon layer on the first amorphous silicon layer containing dopants of predetermined conductivity type therein, opposite the gate electrode insulating layer.

6. The method of claim 3, wherein the step of forming a source/drain electrode comprises the steps of:

forming a first metal layer containing a refractory metal selected from the group consisting of chromium, molybdenum, titanium and tantalum, on the second amorphous silicon layer;

forming a second metal layer containing aluminum, on the first metal layer; and

patterning the first and second metal layers into the source/drain electrode.

7. The method of claim 6, wherein the step of forming a pixel electrode comprises a step of forming a pixel electrode in ohmic contact with a patterned first metal layer.

8. The method of claim 5, wherein the step of forming a first amorphous silicon layer comprises depositing a first amorphous silicon layer having a thickness of about 2000 Å

on the gate electrode insulating layer, wherein the step of forming a second amorphous silicon layer comprises depositing a second amorphous silicon layer containing dopants therein of predetermined conductivity type and having a thickness of about 500 Å

on the first amorphous silicon layer.

9. The method of claim 5, wherein the step of forming a source/drain electrode comprises the step of:

forming the first metal layer having a thickness of about 1000 Å

on the second amorphous silicon layer; and

forming the second metal layer having a thickness of about 2000 Å

on the first metal layer.

10. The method of claim 6, wherein the step of forming the pixel electrode is preceded by the step of wet etching a patterned second metal layer to expose a patterned first metal layer.

11. The method of claim 1, wherein the step of forming the source/drain electrode comprises the steps of:

forming a first metal layer containing a refractory metal selected from the group consisting of chromium, molybdenum, titanium and tantalum, on the semiconductor layer;

forming a second metal layer containing aluminum, on the first metal layer; and

patterning the first and second metal layers into a spaced apart source and drain electrode.

12. The method of claim 11, wherein the step of forming the pixel electrode comprises the step of forming the pixel electrode in ohmic contact with the patterned first metal layer.

13. The method of claim 11, wherein the step of forming the source/drain electrode comprises the steps of:

forming the first metal layer having a thickness of about 1000 Å

on the semiconductor layer; and

forming the second metal layer having a thickness of about 2000 Å

on the first metal layer.

14. The method of claim 11, wherein the step of forming the pixel electrode is preceded by the step of wet etching the patterned second metal layer to expose the patterned first metal layer.