METHOD AND APPARATUS TO INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL

• US 20050158955A1
• Filed: 01/16/2004
• Published: 07/21/2005
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhu, Huilong
• Granted Patent: US 7,118,999 B2
• Time in Patent Office: Days
• US Class Current: 438/282
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.

Claims

1. A method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate, comprising:

depositing a nitride film along a surface of the substrate and the gate stack, wherein the nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack.

2. The method of claim 1, further comprising forming a spacer adjacent only a lower portion of the gate stack.

3. The method of claim 2, wherein forming the spacer comprises reducing a size of the spacer.

4. The method of claim 3, wherein reducing the spacer comprises reactive ion etching.

5. The method of claim 1, wherein the nitride film is a non-conformal nitride film.

6. The method of claim 1, wherein depositing the nitride film comprises a plasma enhanced vapor deposition process.

7. The method of claim 1, wherein the deposition of the nitride film provides enhanced stress within a transistor channel.

8. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate; and

removing the nitride film on the gate stack to provide enhanced stress in a transistor channel under the gate stack.

9. The method of claim 8, further comprising depositing a resist material on a surface of the nitride film over the substrate while leaving a surface of the nitride film proximate an upper portion of the gate stack exposed.

10. The method of claim 9, further comprising removing an upper portion of the gate stack and the nitride film disposed thereon.

11. The method of claim 9, wherein depositing the resist comprises depositing one of a spin-on material, an anti-reflection coating, an oxide film, and a low k material.

12. The method of claim 11, further comprising forming spacers at a lower portion of the sidewalls of the gate stack.

13. The method of claim 11, wherein forming the spacers includes forming the spacers along substantially all of the sidewall and etching the spacers to form spacers at the lower portion of the sidewalls.

14. The method of claim 11, wherein depositing a resist comprises depositing at least one of an oxide layer or a borophosphorosilicate glass on low spots and leaving high spots exposed.

15. The method of claim 10, wherein removing a portion of the gate stack and the nitride film disposed thereon comprises reactive ion etching.

16. The method of claim 10, wherein removing a portion of the gate stack and the nitride film disposed thereon comprises chemical mechanical polishing.

17. The method of claim 8, further comprising forming a spacer adjacent a sidewall of the gate stack and etching upper portions of the spacer to form sidewalls only at a lower portion of the sidewalls.

18. The method of claim 8, wherein the gate is about 60 nm wide, a spacer is about 50 nm wide, and the nitride film provides a stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 4.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide.

19. The method of claim 8, wherein for a semiconductor device having a gate about 60 nm wide, a spacer about 50 nm wide, and a nitride film stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 5.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide.

20-24. -24. (canceled)