System and method for remote asset monitoring

• US 20050159905A1
• Filed: 08/25/2004
• Published: 07/21/2005
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Worldtelemetry, Inc.
• Original Assignee: LPG Central, Inc.
• Inventors: Spencer, Travis J., Zandbergen, Cornelis Jr., Bond, Stuart K., Fate, Joshua R., Gaut, Michael
• Granted Patent: US 7,337,078 B2
• Time in Patent Office: Days
• US Class Current: 702/51
• CPC Class Codes: G01F 15/063 using electrical means
• CPC Class Codes: G01F 23/802 Particular electronic circuits for digital processing equipment
• CPC Class Codes: H04Q 9/00 Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom

Abstract

A system and method for remotely monitoring conditions at a location and for controlling devices at the location. The inventive system includes: a data link in communication with an electronically readable instrument, the data link having a transceiver configured for wireless digital communication; and a data gate having a wireless transceiver configured to communicate with one or more data links, the data gate also having an interface for connection to a communication network such as a land-line telephone network, cellular/pcs network, satellite communication network, or the like. In a preferred embodiment, the data gate communicates with a server via the communication network where the information from the electronically readable instrument is processed and made available to other devices over a computer network.

Claims

1. An asset interface device comprising:

a clock circuit intermittently activating a circuit of said device for a predetermined period of operation;

a sensor circuit communicating with said clock circuit, wherein said sensor circuit is responsive to operational data related to an asset communicating with said asset interface device;

a transceiver circuit communicating with said sensor circuit, wherein said transceiver circuit transmits and receives said operational data during said predetermined period of operation; and

a control circuit communicating with and interposed between said sensor circuit and said transceiver circuit translating said operational data during said predetermined period of operation, wherein said clock circuit, sensor circuit, transceiver circuit, and control circuit are each configured for intrinsically safe operation.

2. The device of claim 1, further comprising a voltage regulation circuit responsive to said clock circuit, wherein upon activation of said voltage regulation circuit by said clock circuit for said predetermined period of operation, said voltage regulation circuit conducts energy to each said sensor, transceiver, and control circuit for operation of said sensor, transceiver, and control circuits.

3. The device of claim 2, further comprising an energy source communicating with said voltage regulation circuit, wherein said energy source provides energy conducted by said voltage regulation circuit to said sensor, transceiver, and control circuits during said predetermined period of operation.

4. The device of claim 3, in which said voltage regulation circuit comprises a capacitor of predetermined capacitance, wherein upon activation of said voltage regulation circuit, said energy source provides energy to said capacitor during said predetermined period of operation to charge said capacitor.

5. The device of claim 4, in which said capacitor communicates with said clock circuit and provides energy to said clock circuit upon deactivation of said voltage regulation circuit by said clock circuit, and continues to provide energy to said clock circuit until reactivation of said voltage regulation circuit by said clock circuit.

6. The device of claim 5, in which said predetermined capacitance of said capacitor is selected to minimize sag in the voltage across said capacitor during deactivation of said voltage regulation circuit.

7. The device of claim 4, further comprises a transmission power adjustment circuit communicating with said control circuit, wherein said transmission power adjustment circuit increases an output power of said transceiver circuit when a signal strength is lower than ideal, and decreases said output power of said transceiver circuit when said signal strength is greater than necessary for good reception.

8. A method for communicating between a transmitting device and a receiving device over a network by steps comprising:

(a) packaging data to be transmitted over said network into a packet at said transmitting device, wherein said packet comprises a plurality of sequential bits;

(b) transmitting said plurality of sequential bits over said network, wherein said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said transmitting device; and

(c) sampling said plurality of sequential bits at said receiving device communicating with said transmitting device, wherein said receiving device samples each bit of said plurality of sequential bits at a predetermined bit sample rate, wherein said predetermined bit sample rate is greater than said predetermined bit transfer rate such that a plurality of samples of each of the plurality of sequential bits are taken during a sample period for each bit of said plurality of sequential bits of said packet.

9. The method of claim 8, by steps further comprising:

(d) constructing a preamble to said plurality of sequential bits at said transmission device, wherein said preamble comprises a predetermined bit pattern; and

(e) detecting said predetermined bit pattern at said receiving device to determine a starting position for said plurality of sequential bits based on said predetermined bit pattern.

10. The method of claim 9, by steps further comprising:

(f) for each bit of said plurality of sequential bits received at said receiving device,

(i) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during a beginning portion of said sample period;

(ii) saving a predetermined number of samples of each bit of said plurality of sequential bits taken during an intermediate portion of said sample period;

(iii) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during an ending portion of said sample period; and

(iv) processing said predetermined number of saved samples of each bit of said plurality of sequential bits to determine a binary state of each bit of said plurality of sequential bits; and

(g) reconstructing said packet from said binary state of each bit of said plurality of sequential bits determined in step (f)(iv).

11. The method of claim 8, in which said predetermined bit sample rate is sixteen times greater than said predetermined bit transfer rate, and by steps further comprising:

(d) for each bit of said plurality of sequential bits received at said receiving device,

(i) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during a beginning portion of said sample period;

(ii) saving a predetermined number of samples of each bit of said plurality of sequential bits taken during an intermediate portion of said sample period;

(iii) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during an ending portion of said sample period; and

(iv) processing said predetermined number of saved samples of each bit of said plurality of sequential bits to determine a binary state of each bit of said plurality of sequential bits; and

(e) reconstructing said packet from said binary state of each bit of said plurality of sequential bits determined in step (d)(iv).

12. The method of claim 11, in which the predetermined number of samples ignored by step (d)(i) is three.

13. The method of claim 11, in which the predetermined number of samples saved by step (d)(ii) is ten.

14. The method of claim 11, in which the predetermined number of samples ignored by step (d)(iii) is three.

15. The method of claim 10, in which the predetermined number of saved samples processed by step (f)(iv) is ten, the predetermined number of samples ignored by step (f)(iii) is three, the predetermined number of samples saved by step (f)(ii) is ten, and the predetermined number of samples ignored by step (f)(i) is three.

16. The method of claim 11, in which said predetermined bit sample rate is sixteen times greater than said predetermined bit transfer rate, the predetermined number of saved samples processed by step (d)(iv) is ten, the predetermined number of samples ignored by step (d)(iii) is three, the predetermined number of samples saved by step (d)(ii) is ten, and the predetermined number of samples ignored by step (d)(i) is three.

17. The method of claim 15, in which said network is wireless.

18. The method of claim 16, in which said network is wireless.

19. A method for communicating over a wireless network between a data link, a data gate, and a server configured to accept HTTP input by steps comprising:

(a) packaging data to be transmitted over said network into a packet at said data link, wherein said packet comprises a plurality of sequential bits;

(b) constructing a preamble to said plurality of sequential bits at said data link, wherein said preamble comprises a predetermined bit pattern;

(c) transmitting said packet with said preamble over a first radio frequency channel from said data link, wherein said preamble and said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said data link;

(d) transmitting said packet with said preamble over a second radio frequency channel from said data link, wherein said preamble and said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said data link;

(e) detecting said predetermined bit pattern at said data gate of said preamble transmitted over said first radio frequency channel to determine a starting position for said plurality of sequential bits based on said predetermined bit pattern;

else

(f) detecting said predetermined bit pattern at said data gate of said preamble transmitted over said second radio frequency channel to determine said starting position for said plurality of sequential bits based on said predetermined bit pattern, when determination of said starting position for said plurality of sequential bits transmitted over said first radio frequency channel fails;

(g) sampling said plurality of sequential bits at said data gate, wherein said data gate samples each bit of said plurality of sequential bits at a predetermined bit sample rate, wherein said predetermined bit sample rate is greater than said predetermined bit transfer rate such that a plurality of samples of each of the plurality of sequential bits are taken during a sample period for each bit of said plurality of sequential bits of said packet; and

(h) transmitting a response packet from said data gate to said data link over said first and second radio frequency channels.

20. The method of claim 19, by steps further comprising:

(i) for each bit of said plurality of sequential bits received at said data gate,

(1) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during a beginning portion of said sample period;

(2) saving a predetermined number of samples of each bit of said plurality of sequential bits taken during an intermediate portion of said sample period;

(3) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during an ending portion of said sample period; and

(4) processing said predetermined number of saved samples of each bit of said plurality of sequential bits to determine a binary state of each bit of said plurality of sequential bits; and

(j) reconstructing said packet from said binary state of each bit of said plurality of sequential bits determined in step (i)(4).

(k) forming a UDP packet including a first header from said reconstructed packet;

(l) transmitting said UDP packet from said data gate to said server; and

(m) executing a program in said server which includes the steps of;

(1) receiving said UDP packet;

(2) expanding data of said UDP packet into an ASCII string;

(3) adding predetermined information to said ASCII string to form a valid HTTP request line; and

(4) submitting said HTTP request line to the server.

21. The method of claim 20, by steps further comprising:

(n) executing a program in said server which includes the steps of;

(1) receiving a response to said HTTP request line;

(2) forming a plurality of UDP response packets from said response, each of said UDP response packets including a second header and response data; and

(3) transmitting said UDP response packets from said server to said data gate; and

(o) receiving said plurality of UDP response packets at said data gate.

22. A system for intrinsically safe monitoring of a volatile materials storage and delivery system comprising:

an asset interface device comprising;

a clock circuit intermittently activating a low quiescent current voltage regulator circuit of said device for a predetermined period of operation;

a capacitor connected to the output of the regulator, wherein said capacitor is charged until a voltage level of said capacitor attains an upper limit during said predetermined period of operation;

a sensor circuit communicating with said clock circuit, wherein said sensor circuit is responsive to operational data related to said volatile materials storage and delivery system;

a transceiver circuit communicating with said sensor circuit, wherein said transceiver circuit transmits and receives said operational data during said predetermined period of operation;

a control circuit communicating with and interposed between said sensor circuit and said transceiver circuit translating said operational data during said predetermined period of operation, wherein said clock circuit, sensor circuit, transceiver circuit, and control circuit are each configured for intrinsically safe operation;

a data transmission repeater communicating with said asset interface device, wherein said data transmission repeater receives said operational data during said predetermined period of operation and retransmits said operational data during said predetermined period of operation;

a data gate communicating with said asset interface device and said data transmission repeater, said data gate detects said transmitted operational data during said predetermined period of operation and retransmits said operational data; and

a server communicating with said data gate, wherein said server receives said operational data from said data gate and transmits operational data to said data gate for management of said volatile materials storage and delivery system, wherein said volatile materials storage and delivery system includes a controllable device communicating with said asset interface device to effect said management of said volatile materials storage and delivery system, and wherein transmission of said operational data is transmitted by steps for communicating over a wireless network between said asset interface device, said data gate, and said server, wherein said server is configured to accept HTTP protocol.

23. The system of claim 22, in which said steps for communicating over said wireless network between said asset interface device, said data gate, and said server configured to accept HTTP protocol comprise:

(a) packaging said operational data to be transmitted over said network into a packet at said asset interface device, wherein said packet comprises a plurality of sequential bits;

(b) constructing a preamble to said plurality of sequential bits at said asset interface device, wherein said preamble comprises a predetermined bit pattern;

(c) transmitting said packet with said preamble over a first radio frequency channel from said asset interface device, wherein said preamble and said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said asset interface device;

(d) transmitting said packet with said preamble over a second radio frequency channel from said asset interface device, wherein said preamble and said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said asset interface device;

(e) detecting said predetermined bit pattern at said data gate of said preamble transmitted over said first radio frequency channel to determine a starting position for said plurality of sequential bits based on said predetermined bit pattern;

else

(f) detecting said predetermined bit pattern at said data gate of said preamble transmitted over said second radio frequency channel to determine said starting position for said plurality of sequential bits based on said predetermined bit pattern, when determination of said starting position for said plurality of sequential bits transmitted over said first radio frequency channel fails;

(g) sampling said plurality of sequential bits at said data gate, wherein said data gate samples each bit of said plurality of sequential bits at a predetermined bit sample rate, wherein said predetermined bit sample rate is greater than said predetermined bit transfer rate such that a plurality of samples of each of the plurality of sequential bits are taken during a sample period for each bit of said plurality of sequential bits of said packet; and

(h) transmitting a response packet from said data gate to said asset interface device over said first and second radio frequency channels.

24. The system of claim 23, in which said steps for communicating over said wireless network between said asset interface device, said data gate, and said server configured to accept HTTP protocol further comprise:

(i) for each bit of said plurality of sequential bits received at said data gate,

(1) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during a beginning portion of said sample period;

(2) saving a predetermined number of samples of each bit of said plurality of sequential bits taken during an intermediate portion of said sample period;

(3) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during an ending portion of said sample period; and

(4) processing said predetermined number of saved samples of each bit of said plurality of sequential bits to determine a binary state of each bit of said plurality of sequential bits; and

(j) reconstructing said packet from said binary state of each bit of said plurality of sequential bits determined in step (i)(4).

(k) forming a UDP packet including a first header from said reconstructed packet;

(l) transmitting said UDP packet from said data gate to said server; and

(m) executing a program in said server which includes the steps of;

(1) receiving said UDP packet;

(2) expanding data of said UDP packet into an ASCII string;

(3) adding predetermined information to said ASCII string to form a valid HTTP request line; and

(4) submitting said HTTP request line to the server.

25. The system of claim 22, in which upon activation of said low quiescent current voltage regulator circuit by said clock circuit for said predetermined period of operation, said low quiescent current voltage regulator circuit conducts energy to each said sensor, transceiver, and control circuit for operation of said sensor, transceiver, and control circuits.

26. The system of claim 25, further comprising an energy source communicating with said low quiescent current voltage regulator circuit, wherein said energy source provides energy conducted by said low quiescent current voltage regulator circuit to said sensor, transceiver, and control circuits during said predetermined period of operation.

27. The system of claim 26, in which said capacitor communicates with said clock circuit and provides energy to said clock circuit upon deactivation of said low quiescent current voltage regulator circuit by said clock circuit, and continues to provide energy to said clock circuit until reactivation of said low quiescent current voltage regulator circuit by said clock circuit.

28. The system of claim 27, in which said capacitor is selected to minimize sag in the voltage across said capacitor during deactivation of said low quiescent current voltage regulator circuit.

29. The system of claim 22, further comprises a transmission power adjustment circuit communicating with said control circuit, wherein said transmission power adjustment circuit increases an output power of said transceiver circuit when a signal strength is lower than ideal, and decreases said output power of said transceiver circuit when said signal strength is greater than necessary for good reception.

30. The system of claim 22, in which the repeater comprises a solar panel.

31. A system for intrinsically safe monitoring of leakage of an underground storage tank comprising:

an asset interface device comprising;

a clock circuit intermittently activating a low quiescent current voltage regulator circuit of said device for a predetermined period of operation;

a capacitor connected to the output of the regulator, wherein said capacitor is charged until a voltage level of said capacitor attains an upper limit during said predetermined period of operation;

a sensor circuit communicating with said clock circuit, wherein said sensor circuit is responsive to operational data related to said volatile materials storage and delivery system;

a transceiver circuit communicating with said sensor circuit, wherein said transceiver circuit transmits and receives said operational data during said predetermined period of operation;

a control circuit communicating with and interposed between said sensor circuit and said transceiver circuit translating said operational data during said predetermined period of operation, wherein said clock circuit, sensor circuit, transceiver circuit, and control circuit are each configured for intrinsically safe operation;

a data transmission repeater communicating with said asset interface device, wherein said data transmission repeater receives said operational data during said predetermined period of operation and retransmits said operational data during said predetermined period of operation;

a data gate communicating with said asset interface device and said data transmission repeater, said data gate detects said transmitted operational data during said predetermined period of operation and retransmits said operational data; and

a server communicating with said data gate, wherein said server receives said operational data from said data gate and transmits operational data to said data gate for management of said volatile materials storage and delivery system, wherein said volatile materials storage and delivery system includes a controllable device communicating with said asset interface device to effect said management of said volatile materials storage and delivery system, and wherein transmission of said operational data is transmitted by steps for communicating over a wireless network between said asset interface device, said data gate, and said server, wherein said server is configured to accept HTTP protocol.

32. The system of claim 31, in which said steps for communicating over said wireless network between said asset interface device, said data gate, and said server configured to accept HTTP protocol comprise:

(a) packaging said operational data to be transmitted over said network into a packet at said asset interface device, wherein said packet comprises a plurality of sequential bits;

(b) constructing a preamble to said plurality of sequential bits at said asset interface device, wherein said preamble comprises a predetermined bit pattern;

(c) transmitting said packet with said preamble over a first radio frequency channel from said asset interface device, wherein said preamble and said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said asset interface device;

(d) transmitting said packet with said preamble over a second radio frequency channel from said asset interface device, wherein said preamble and said plurality of sequential bits are transmitted at a predetermined bit transfer rate by said asset interface device;

(e) detecting said predetermined bit pattern at said data gate of said preamble transmitted over said first radio frequency channel to determine a starting position for said plurality of sequential bits based on said predetermined bit pattern;

else

(f) detecting said predetermined bit pattern at said data gate of said preamble transmitted over said second radio frequency channel to determine said starting position for said plurality of sequential bits based on said predetermined bit pattern, when determination of said starting position for said plurality of sequential bits transmitted over said first radio frequency channel fails;

(g) sampling said plurality of sequential bits at said data gate, wherein said data gate samples each bit of said plurality of sequential bits at a predetermined bit sample rate, wherein said predetermined bit sample rate is greater than said predetermined bit transfer rate such that a plurality of samples of each of the plurality of sequential bits are taken during a sample period for each bit of said plurality of sequential bits of said packet; and

(h) transmitting a response packet from said data gate to said asset interface device over said first and second radio frequency channels.

33. The system of claim 32, in which said steps for communicating over said wireless network between said asset interface device, said data gate, and said server configured to accept HTTP protocol further comprise:

(i) for each bit of said plurality of sequential bits received at said data gate,

(1) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during a beginning portion of said sample period;

(2) saving a predetermined number of samples of each bit of said plurality of sequential bits taken during an intermediate portion of said sample period;

(3) ignoring a predetermined number of samples of each bit of said plurality of sequential bits taken during an ending portion of said sample period; and

(4) processing said predetermined number of saved samples of each bit of said plurality of sequential bits to determine a binary state of each bit of said plurality of sequential bits; and

(j) reconstructing said packet from said binary state of each bit of said plurality of sequential bits determined in step (i)(4).

(k) forming a UDP packet including a first header from said reconstructed packet;

(l) transmitting said UDP packet from said data gate to said server; and

(m) executing a program in said server which includes the steps of;

(1) receiving said UDP packet;

(2) expanding data of said UDP packet into an ASCII string;

(3) adding predetermined information to said ASCII string to form a valid HTTP request line; and

(4) submitting said HTTP request line to the server.

34. The system of claim 31, in which upon activation of said low quiescent current voltage regulator circuit by said clock circuit for said predetermined period of operation, said low quiescent current voltage regulator circuit conducts energy to each said sensor, transceiver, and control circuit for operation of said sensor, transceiver, and control circuits.

35. The system of claim 34, further comprising an energy source communicating with said low quiescent current voltage regulator circuit, wherein said energy source provides energy conducted by said low quiescent current voltage regulator circuit to said sensor, transceiver, and control circuits during said predetermined period of operation.

36. The system of claim 35, in which said capacitor communicates with said clock circuit and provides energy to said clock circuit upon deactivation of said low quiescent current voltage regulator circuit by said clock circuit, and continues to provide energy to said clock circuit until reactivation of said low quiescent current voltage regulator circuit by said clock circuit.

37. The system of claim 36, in which said capacitor is selected to minimize sag in the voltage across said capacitor during deactivation of said low quiescent current voltage regulator circuit.

38. The system of claim 31, further comprises a transmission power adjustment circuit communicating with said control circuit, wherein said transmission power adjustment circuit increases an output power of said transceiver circuit when a signal strength is lower than ideal, and decreases said output power of said transceiver circuit when said signal strength is greater than necessary for good reception.

39. The system of claim 31, in which the repeater comprises a solar panel.