Method and device for controlling a memory access

• US 20050160246A1
• Filed: 12/22/2004
• Published: 07/21/2005
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Tdk-Micronas Gmbh (TDK Corporation)
• Original Assignee: Micranos GmbH
• Inventors: Franke, Joerg
• Granted Patent: US 7,747,832 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is made possible in that the number of waiting states for the memory access is established individually as a function of an analysis of an instantaneous state (status) of the central control unit (CPU) and/or a type and/or address of the storage device (FLASH/ROM, RAM, IO module) being accessed.

Claims

1. Method for controlling a memory access, wherein

a number of waiting states is determined for the memory access to a storage device (FLASH/ROM, RAM, IO-Module) for a central control unit CPU, characterized in that,

the number of waiting states for the memory access is determined individually, depending on an analysis of a current state (status) of the central control unit CPU and/or a type and/or address adr of the storage device being accessed (FLASH/ROM, RAM, IO-Module).

2. Method according to claim 1, in which the determining of the number of required waiting states is done in a memory control unit aMC, which is separate from the central control unit (CPU), and the waiting states of the central control unit (CPU) are signaled by means of a waiting state signal (wait).

3. Method according to claim 1, in which a maximum number (limit) of required waiting states is determined when analyzing and establishing the number of necessary waiting states for the type of memory access and/or the type of storage device being accessed and used in a waiting state counter (WC).

4. Method according to claim 1, in which an address (adr) is used for the analysis that is set by the central control unit (CPU) on an address bus (AB) for addressing the at least one storage device.

5. Method according to claim 1, in which an address comparator (AC) compares a current address (A2, A3;

A0+1, A0+2) with an address (A1;

A0) present at an earlier time, especially one immediately prior, to determine whether they are addresses (A1, A2, A3) on a same storage page, incremented addresses (A0, A0+1, A0+2) and/or same addresses, and in such a case the number of required waiting states is reduced as compared to other cases.

6. Method according to claim 1, in which an address comparator (AC) compares a current address (RAM, EX+1, EX+2) with an address (EX) that was present at an earlier time, especially one immediately prior, to determine whether the currently present address is assigned to a storage device (RAM) without required waiting states and the address (EX, EX+1) prior and subsequent to it is an address of a storage device (FLASH/ROM) with required waiting states assigned, in which case the number of required waiting states is reduced as compared to other cases, especially the number of waiting states is reduced for memory access with required waiting states if the memory accesses to the storage device with required waiting states involve incrementing addresses, same addresses, or addresses of the same memory page.

7. Method according to claim 6, in which a memory control unit (aMC) in the cycle of the memory access to the storage device (RAM) already by itself generates an additional address (EX+1) and provides it to the external storage device.

8. Method according to claim 1, wherein in the case of internal cycles of the central control unit (CPU), memory accesses to an already present address (A0) to be used in future are carried out independently by the central control unit (CPU), in order to transfer corresponding data without waiting states after the end of the internal cycle.

9. Method according to claim 1, wherein the width of a bus (DB) to the storage device is larger than the width of the data from the storage unit that is required by the central control unit, and wherein in this case the number of waiting states is reduced corresponding to a more tightly clocked data transfer.

10. Method according to claim 9, wherein a bridge device (BR) between data bus (DB) and the storage device (IO module) is occupied by consecutive addresses (A0, A0+2, A0+4), from which intermediate addresses are omitted, and in addition a signaling (byte-adr) is used to address the omitted addresses.

11. Method according to claim 1, wherein in the case of a memory access to a storage device with various levels of page and/or burst access types, to which different access times are assigned, corresponding maximum required waiting states are established for the individual memory accesses.

12. Method according to claim 1, wherein in the case of a memory access to an open page, the number of waiting states is reduced in comparison to the access to a not-open page.

13. Method according to claim 1, wherein to determine the number of required waiting states in a storage device (M) of a memory control unit (aMC) in order to carry out the method, properties of accessible storage devices and/or accessible addresses with respectively assigned required waiting times are saved in memory.

14. Device (aMC) for controlling a memory access, with a first connection to a central control unit (CPU) for transfer of first data and/or signals (status, wait), comprising:

a second connection (AB) for transfer of second data or signals (adr) regarding a storage device being accessed (FLASH/ROM, RAM, IO module), and

a control unit for controlling the memory access to the storage device and to establish waiting states for the central control unit (CPU)

wherein the control unit (aMC;

AD, AC, MD, CL, WC, BC) is configured to analyze the first data (status) with regard to the state of the central control unit (CPU) and/or the second data (adr) regarding the storage device being accessed, and to establish the corresponding waiting states and signal (wait) the waiting states to the central control unit (CPU).

15. Device according to claim 14 comprising a storage device (M) or a connection to a storage device for saving of waiting states in memory, which are assigned to addresses and/or storage devices where such a memory access can occur.

16. Device according to claim 14 comprising a waiting state counter (WC) for incrementing up to a limit value (limit) corresponding to the required memory access and with a configuration logic (CL) for signaling a waiting state signal (wait), dependent upon reaching the limit value (limit) in the waiting state counter (WC) and independent of an analysis of an address being accessed.