Method and apparatus of controlling electric power for translation lookaside buffer

• US 20050160250A1
• Filed: 03/11/2005
• Published: 07/21/2005
• Est. Priority Date: 05/21/2003
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshimi, Koichi
• Granted Patent: US 7,418,553 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention is intended to reduce unnecessary power consumption by controlling disconnection of entries unused in a translation lookaside buffer (TLB) for a long time. In an aspect of the present invention, there is provided a method of controlling electric power consumed for a translation lookaside buffer (TLB) within a central processing device having the TLB and an entry replacement mechanism wherein the TLB includes a plurality of entries and performs translation from a logical address to a physical address and the entry replacement mechanism replaces the entries of the TLB, the method including the steps of: selecting one or more entries among the plurality of entries of the TLB in accordance with one or more predefined criteria based on an output from the entry replacement mechanism, and controlling electric power supplied to the selected entries.

Claims

1. A method of controlling electric power consumed for a translation lookaside buffer (TLB) within a central processing device having the TLB and an entry replacement mechanism wherein the TLB includes a plurality of entries and performs translation from a logical address to a physical address and the entry replacement mechanism replaces the entries of the TLB, the method comprising the steps of:

selecting one or more entries among the plurality of entries of the TLB in accordance with one or more predefined criteria based on an output from the entry replacement mechanism, and

controlling electric power supplied to the selected entries.

2. The method as claimed in claim 1, wherein the output from the entry replacement mechanism is replacement order information on the plurality of entries.

3. The method as claimed in claim 2, wherein the replacement order information is based on use frequency of each of the plurality of entries.

4. The method as claimed in claim 1, further comprising the step of:

inputting information for controlling for the entry selection step to select second through n-th entries in accordance with the replacement order information.

5. The method as claimed in claim 1, wherein the predefined criteria comprises one or more of size information on memory pages used by the central processing device, priority level information on keeping an entry of an address translation table specified in unit of process executed by the central processing device, access interval information to the address translation table, replacement order information and information for controlling to select second through n-th entries in accordance with the replacement order information.

6. The method as claimed in claim 1, further comprising the step of:

inputting selectivity information and weight information,

wherein the selectivity information is for determining whether to use as the predefined criteria one or more of the size information on memory pages used by the central processing device, the priority level information on keeping an entry of an address translation table specified in unit of process executed by the central processing device, the access interval information to the address translation table, the replacement order information and the information for controlling to select second through n-th entries in accordance with the replacement order information, and the weight information is associated with weighting of the one or more information.

7. A apparatus for controlling electric power consumed for a translation lookaside buffer (TLB) within a central processing device having the TLB and an entry replacement mechanism wherein the TLB includes a plurality of entries and performs translation from a logical address to a physical address and the entry replacement mechanism replaces the entries of the TLB, the apparatus comprising:

an entry selection part selecting one or more entries among the plurality of entries of the TLB in accordance with one or more predefined criteria based on an output from the entry replacement mechanism, and

a power control part controlling electric power supplied to the selected entries.

8. The apparatus as claimed in claim 7, wherein the output from the entry replacement mechanism is replacement order information on the plurality of entries.

9. The apparatus as claimed in claim 8, wherein the replacement order information is based on use frequency of each of the plurality of entries.

10. The apparatus as claimed in claim 7, further comprising:

an information input part inputting information for controlling for the entry selection part to select second through n-th entries in accordance with the replacement order information.

11. The apparatus as claimed in claim 7, wherein the predefined criteria comprises one or more of size information on memory pages used by the central processing device, priority level information on keeping an entry of an address translation table specified in unit of process executed by the central processing device, access interval information to the address translation table, replacement order information and information for controlling to select second through n-th entries in accordance with the replacement order information.

12. The apparatus as claimed in claim 7, further comprising:

an input part inputting selectivity information and weight information,

wherein the selectivity information is for determining whether to use as the predefined criteria one or more of the size information on memory pages used by the central processing device, the priority level information on keeping an entry of an address translation table specified in unit of process executed by the central processing device, the access interval information to the address translation table, the replacement order information and the information for controlling to select second through n-th entries in accordance with the replacement order information, and the weight information is associated with weighting of the one or more information.

13. A central processing device, comprising:

a translation lookaside buffer (TLB) having a plurality of entries and performing translation from a logical address to a physical address;

an entry replacement mechanism replacing one or more of the plurality of entries of the TLB; and

a device including an entry selection part selecting one or more entries among the plurality of entries of the TLB in accordance with one or more predefined criteria based on an output from the entry replacement mechanism, and a power control part controlling electric power supplied to the selected entries.