Mechanism for reducing write problems by controlling charge pumps for flash memory
First Claim
1. An integrated circuit comprising a processor, a memory that the processor can access, a memory access unit for controlling accesses to the memory, an input for receiving power for the integrated circuit from an external power source, and a power detection unit, the power detection unit being configured to:
- monitor a quality of power supplied to the input;
in the event the quality of the power drops below a predetermined threshold, disabling a power supply to circuitry for use in writing to the memory, such that the memory access unit'"'"'s ability to alter data in the memory is disabled prior to address or data values to be written to the memory becoming unreliable due to failing power.
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Accused Products
Abstract
An integrated circuit comprising a processor, a memory that the processor can access, a memory access unit for controlling accesses to the memory, an input for receiving power for the integrated circuit from an external power source, and a power detection unit, the power detection unit being configured to: monitor a quality of power supplied to the input; and in the event the quality of the power drops below a predetermined threshold, disabling a power supply to circuitry for use in writing to the memory, such that the memory access unit'"'"'s ability to alter data in the memory is disabled prior to address or data values to be written to the memory becoming unreliable due to failing power.
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Citations
5 Claims
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1. An integrated circuit comprising a processor, a memory that the processor can access, a memory access unit for controlling accesses to the memory, an input for receiving power for the integrated circuit from an external power source, and a power detection unit, the power detection unit being configured to:
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monitor a quality of power supplied to the input;
in the event the quality of the power drops below a predetermined threshold, disabling a power supply to circuitry for use in writing to the memory, such that the memory access unit'"'"'s ability to alter data in the memory is disabled prior to address or data values to be written to the memory becoming unreliable due to failing power. - View Dependent Claims (2, 3, 4, 5)
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Specification