Method and apparatus for adding advanced instructions in an extensible processor architecture

• US 20050160402A1
• Filed: 05/13/2002
• Published: 07/21/2005
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: Tensilica Incorporated
• Original Assignee: Tensilica Incorporated
• Inventors: Killian, Earl A., Wang, Albert R., Wilson, Robert P., Gonzalez, Ricardo E.
• Granted Patent: US 7,346,881 B2
• Time in Patent Office: Days
• US Class Current: 717/114
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load/store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.

Claims

1. A processor extension language that enables the description of VLIW instructions for execution by corresponding logic in addition to core instructions for execution by a microprocessor core, the description including a configurable characteristic of the VLIW instructions.

2. A processor extension language according to claim 1, wherein the configurable characteristic comprises instruction length.

3. A processor extension language according to claim 1, wherein the configurable characteristic comprises instruction format.

4. A processor extension language according to claim 1, wherein the configurable characteristic comprises the number of operation slots per instruction.

5. A processor extension language according to claim 1, wherein the configurable characteristic comprises instruction fields.

6. A processor extension language according to claim 1, wherein the configurable characteristic comprises instruction opcodes.

7. A processor extension language according to claim 1, wherein the configurable characteristic comprises instruction operations.

8. A processor extension language that enables the description of load/store instructions for execution by corresponding logic in addition to core instructions for execution by a microprocessor core, the description including a configurable word manipulation that is automatically performed in conjunction with the load/store instructions.

9. A processor extension language according to claim 8, wherein the configurable word manipulation comprises a load/store byte-disable interface.

10. A processor extension language according to claim 8, wherein the configurable word manipulation comprises a rotate-amount interface.

11. A processor extension language according to claim 8, wherein the configurable word manipulation comprises a sign-extension interface.

12. A processor extension language according to claim 8, wherein the configurable word manipulation comprises a conditional load/store interface.

13. A processor extension language according to claim 8, wherein the configurable word manipulation comprises a multiple load/store unit interface.

14. A processor extension language that enables the description of complex instructions for execution by corresponding logic in addition to core instructions for execution by a microprocessor core, the description including a configurable function definition.

15. A processor extension language according to claim 14, wherein the configurable function definition allows different complex instructions to share the same corresponding logic.

16. A processor extension language according to claim 14, wherein the configurable function definition allows iterative execution of the complex instructions.

17. A processor extension language that enables the description of enhanced register file instructions for execution by corresponding logic in addition to core instructions for execution by a microprocessor core, the description including a configurable operand register interface.

18. A processor extension language according to claim 17, wherein the configurable operand register interface comprises multiple read/write widths.

19. A processor extension language according to claim 17, wherein the configurable operand register interface comprises manual binding of operands to register file ports.

20. A processor extension language according to claim 17, wherein the configurable operand register interface comprises register file operand semantics.

21. A processor extension language according to claim 17, wherein the configurable operand register interface comprises an implicit register file operand.

22. A processor extension language that enables the description of exceptions that are raised during execution of instructions by corresponding extension logic in addition to core instructions for execution by a microprocessor core.

23. A processor extension language according to claim 22, wherein the description comprises an exception definition.

24. A processor extension language according to claim 22, wherein the description comprises instruction semantics.

25. A processor extension language according to claim 22, wherein the description comprises operand semantics.

26. A processor extension language according to claim 22, wherein the description comprises exception semantics.

27. A processor extension language according to claim 22, wherein the description comprises support for resolving multiple exceptions.

28. A processor extension language that enables the description of complex instructions for execution by corresponding hardware logic in addition to core instructions for execution by a microprocessor core, wherein the description comprises a built-in module definition that is part of the processor extension language, the module definition being one of an addition with carry-in module, an N-number addition module, a carry-save adder module, a signed and unsigned comparison module, a multiply-accumulate module, a multiply module, a partial-product multiply module, a n-way multiplexor module, a n-way priority selector module, and a n-way 1-hot selector module.