Vertical gate semiconductor device and method for fabricating the same

• US 20050161734A1
• Filed: 12/21/2004
• Published: 07/28/2005
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mizokuchi, Shuji, Miyata, Satoe
• Granted Patent: US 7,372,088 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A source region is formed by performing ion implantation plural times to diffuse an impurity from the upper surface of a semiconductor region toward a region far dawn therefrom and to increase impurity concentration in the vicinity of the upper surface of the semiconductor region, whereby the source region and a gate electrode are overlapped with each other surely. Thus, offset between the gate and the source is prevented and an excellent ohmic contact is formed between a source electrode and the source region.

Claims

1. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said drench.

2. The semiconductor device of claim 1, wherein

said drain region includes:

a first conductivity type high concentration drain region; and

a first conductivity type low concentration drain region provided on said high concentration drain region.

3. The semiconductor device of claim 1, further comprising:

a source electrode provided above said second source region.

4. The semiconductor device of claim 3, wherein

said source electrode is provided at a part above said second source region and on a part where said second source region is exposed at the side surface of said trench, and

a peak of impurity concentration of said second source region appears within a level range of a height of said source electrode provided on the side surface of said trench.

5. The semiconductor device of claim 3, wherein

a silicide film is provided between said second source region and said source electrode.

6. The semiconductor device of claim 1, wherein

an upper end of a part where said gate electrode is in contact with said gate insulating film is located upper than a boundary between said first source region and said body region.

7. The semiconductor device of claim 1, wherein

an upper end of said insulating film is located lower than a peak of impurity concentration of said second source region.

8. The semiconductor device of claim 1, wherein

a second conductivity type impurity region in contact with said body region is provided in a region located on respective sides of said first source region and said second source region in said semiconductor region, and

respective side surfaces of said first source region and said second source region are surrounded by said trench and said impurity region.

9. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type source region provided on said body region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provide on at least a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said trench,

wherein an upper end of said insulating film is located lower than the upper surface of said semiconductor region, and

an impurity concentration of a part of said source region from the upper end of said insulating film to the upper surface of said semiconductor region is equal to or larger than 1×

10²⁰ atoms/cm³.

10. The semiconductor device of claim 9, wherein

said drain region includes:

a first conductivity type high concentration drain region; and

a first conductivity type low concentration drain region provided on said high concentration drain region.

11. The semiconductor device of claim 9, further comprising:

a source electrode provided above said second source region.

12. The semiconductor device of claim 11, wherein

said source electrode is provided at a part above said source region and on a part where said source region is exposed at the side surface of said trench, and

a peak of impurity concentration of said source region appears within a level range of a height of said source electrode provided on the side surface of said trench.

13. The semiconductor device of claim 11, wherein

a silicide film is provided between said source region and said source electrode.

14. The semiconductor device of claim 9, wherein

an upper end of a part where said gate electrode is in contact with said gate insulating film is located upper than a boundary between said source region and said body region.

15. The semiconductor device of claim 9, wherein

the upper end of said insulating film is located lower than a peak of impurity concentration of said source region.

16. The semiconductor device of claim 9, wherein

a second conductivity type impurity region in contact with said body region is provided in a region located on a side of said source region in said semiconductor region, and

a side surface of said source region is surrounded by said trench and said impurity region.

17. A method for fabricating a semiconductor device, comprising the steps of:

a step (a) of preparing a semiconductor region including a drain region and a second conductivity type body region provided on said drain region;

a step (b) of forming a trench in said semiconductor region so as to reach said drain region;

a step (c) of forming, after said step (b), a gate insulating film on at least a side surface of said trench where said semiconductor region is exposed;

a step (d) of forming, after said step (c), a gate electrode on said gate insulating film in said trench;

a step (e) of forming, after said step (d), an insulating film on said gate electrode in said trench;

a step (f) of forming, after said step (b), a first conductivity type first source region on said body region by ion implantation of a first conductivity type impurity to said semiconductor region;

a step (g) of forming, after said step (b), a first conductivity type second source region on said first source region so as to extend to an upper surface of said semiconductor region by ion implantation of a first conductivity type impurity to said semiconductor region.

18. The semiconductor device fabricating method of claim 17, further comprising the step of:

a step (h) of forming a source electrode above said second source region after said step (e), said step (f) and said step (g).

19. The semiconductor device fabricating method of claim 18, wherein

in said step (h), said source electrode is formed also on a part of the side surface of said trench where said second source region is exposed and a peak of impurity concentration of said second source region is arranged so as to appear in a level range of a height of said source electrode provided on the side surface of said trench.

20. The semiconductor device fabricating method of claim 18, further comprising the step of:

forming a silicide film on said second source region after said step (e), said step (f) and said step (g) and before said step (h),

wherein in step (h), said source electrode is formed on said silicide film.

21. The semiconductor device fabricating method of claim 17, wherein

in said step (a), a first conductivity type high concentration region provided in a lower part of said semiconductor region and a first conductivity type low concentration drain region provided on said high concentration drain region are prepared as said drain region.

22. The semiconductor device fabricating method of claim 17, wherein

in said step (f), said ion implantation is performed so that a boundary between said first source region and said body region is located lower than an upper end of a part where said gate electrode is in contact with said gate insulating film.

23. The semiconductor device fabricating method of claim 17, wherein

in said step (g), said ion implantation is performed so that a peak of impurity concentration of said second source region is located higher than an upper end of said insulating film.

24. The semiconductor device fabricating method of claim 17, further comprising the step of:

a step (i) of forming, after said step (a), a second conductivity type impurity region in a region located on respective sides of said first source region and said second source region in said semiconductor region so as to extend from the upper surface of said semiconductor region to said body region,

wherein respective side surfaces of said first source region and said second source region are surrounded by said trench and said impurity region.

25. A method for fabricating a semiconductor device, comprising the steps of:

a step (a) of preparing a semiconductor region including a drain region and a second conductivity type body region provided on said drain region;

a step (b) of forming a trench in said semiconductor region so as to reach said drain region;

a step (c) of forming, after said step (b), a gate insulating film on at least a side surface of said trench where said semiconductor region is exposed;

a step (d) of forming, after said step (c), a gate electrode on said gate insulating film in said trench;

a step (e) of forming, after said step (d), an insulating film on said gate electrode in said trench;

a step (j) of forming, after said step (b), a first conductivity type source region on said body region by performing ion implantation of a first conductivity type impurity at least three times to said semiconductor region,

wherein an upper end of said insulating film is located lower than an upper surface of said semiconductor region, and

impurity concentration of a part of said source region from the upper end of said insulating film to the upper surface of said semiconductor region is equal to or larger than 1×

10²⁰ atoms/cm³.

26. The semiconductor device fabricating method of claim 25, further comprising the step of:

a step (k) of forming a source electrode above said source region after said step (e) and said step (j).

27. The semiconductor device fabricating method of claim 26, wherein

in said step (k), said source electrode is formed also on a part of the side surface of said trench where said source region is exposed and a peak of impurity concentration of said source region is arranged so as to appear in a level range of a height of said source electrode provided on the side surface of said trench.

28. The semiconductor device fabricating method of claim 26, further comprising the step of:

forming a silicide film on said source region after said step (e) and said step (j) and before said step (k),

wherein in step (k), said source electrode is formed on said silicide film.

29. The semiconductor device fabricating method of claim 25, wherein

in said step (a), a first conductivity type high concentration region provided in a lower part of said semiconductor region and a first conductivity type low concentration drain region provided on said high concentration drain region are prepared as said drain region.

30. The semiconductor device fabricating method of claim 25, wherein

in said step (j), said ion implantation is performed so that a boundary between said source region and said body region is located lower than an upper end of a part where said gate electrode is in contact with said gate insulating film.

31. The semiconductor device fabricating method of claim 25, wherein

in said step (j), said ion implantation is performed so that a peak of impurity concentration of said source region is located higher than an upper end of said insulating film.

32. The semiconductor device fabricating method of claim 25, further comprising the step of:

a step (l) of forming, after said step (a), a second conductivity type impurity region in a region located on a side of said source region in said semiconductor region so as to extend from then upper surface of said semiconductor region to said body region,

wherein a side surface of said source region is surrounded by said trench and said impurity region.