Method of producing a semiconductor device

• US 20050161735A1
• Filed: 03/24/2005
• Published: 07/28/2005
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tsuzuki, Yukio, Aoki, Takaaki
• Granted Patent: US 7,026,215 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.

Claims

1-16. -16. (canceled)

17. A method of producing a semiconductor device, comprising the steps of:

forming a trench in a surface portion of a semiconductor substrate so as to extend from a cell-to-be-formed region for forming a cell for operating as a transistor to a gate-lead-wiring-to-be-formed region;

forming an oxide film on an inner surface of the trench so as to have sidewalls and a bottom wall by thermal oxidation; and

forming a gate electrode in the trench insulated with at least the oxide film from the substrate,

wherein, in the step of forming the trench, the trench is formed to have crystal planes of a first main portion of the sidewalls of the trench at the cell-to-be-formed region and a second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region in such a manner that a first speed of forming the oxide film at the cell-to-be-formed region is smaller than a second speed of forming the oxide film at the gate-lead-wiring-to-be-formed region, and

wherein, in the step of forming the oxide film, the thermal oxidation is performed so as to make a first thickness of the oxide film on the inner surface of the trench at the cell-to-be-formed region thinner than a second thickness of the oxide film on the inner surface of the trench at the gate-lead-wiring-to-be-formed region.

18. The method according to claim 17,

wherein the substrate includes a silicon substrate having a (100) crystal plane,

wherein the first main portion of the sidewalls of the trench at the c ell-to-be-formed region has the (100) crystal plane, and

wherein the second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region has a (110) crystal plane.

19. The method according to claim 17,

wherein the substrate includes a silicon substrate having a (110) crystal plane,

wherein the first main portion of the sidewalls of the trench at the c ell-to-be-formed region has a (100) crystal plane, and

wherein the second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region has the (110) crystal plane.

20. The method according to claim 17,

wherein the substrate includes a silicon substrate having a (110) crystal plane,

wherein the first main portion of the sidewalls of the trench at the c ell-to-be-formed region has a (100) crystal plane, and

wherein the second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region has a (111) crystal plane.

21. The method according to claim 17,

wherein the trench at the cell-to-be-formed region provides a quadrangle cell, and

wherein a plurality of cells is arranged on the surface of the semiconductor substrate like a net pattern at the cell region.

22. The method according to claim 17,

wherein the trench at the cell-to-be-formed region provides a hexagon cell, and

wherein a plurality of cells is arranged on the surface of the semiconductor substrate like a net pattern at the cell region.

23. The method according to claim 17,

wherein the trench at the cell-to-be-formed region provides a octagon cell as a first cell and a quadrangle cell as a second cell, and

wherein a plurality of first and second cells is alternately arranged on the surface of the semiconductor substrate like a net pattern at the cell region.

24. The method according to claim 18,

wherein, in the step of forming the oxide film, the thermal oxidation is performed at a temperature between 850°

C. and 1000°

C.

25-29. -29. (canceled)