Multiple die interconnect system

• US 20050161797A1
• Filed: 03/25/2005
• Published: 07/28/2005
• Est. Priority Date: 10/03/2001
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Granted Patent: US 7,681,309 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 7/1092 : with built-in components, e.g. intelligent sockets
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base
• CPC Class Codes: Y10T 29/49149 : by metal fusion bonding
• CPC Class Codes: Y10T 29/53174 : Means to fasten electrical component to wiring board, base, or substrate
• CPC Class Codes: Y10T 29/53178 : Chip component

Abstract

A multiple integrated circuit (IC) die assembly includes a base IC die and secondary IC dice mounted on a surface of the base IC die. A set of protruding contacts formed on the surface of the base IC die and extending beyond the secondary IC dice link the surface of the base IC die to a printed circuit board (PCB) substrate with the secondary IC die residing between the base IC die and the PCB substrate.

Claims

1. A method for interconnecting an integrated circuit (IC) multiple die assembly to conductors on a substrate for conveying signals there between, wherein the multiple die assembly includes a base IC die having a surface and includes at least one secondary IC die mounted on the surface of the base IC die with signal paths provided therebetween, the method comprising the steps of:

a. providing conductive contacts on the surface of the base IC die, each conductive contact having a free end extending outward from the first surface beyond the secondary IC die; and

b. mounting the multiple die assembly on the substrate such that the free end of each contact is brought into contact with the conductors on the substrate and such that the secondary IC resides between the surface of the base IC die and the substrate, wherein the contacts convey the signals between the base IC die and the conductors on the substrate.

2. The method in accordance with claim 1 wherein step b further comprises soldering the free ends of the conductive contacts to the conductors on the substrate and the surface of the substrate.

3. The method in accordance with claim 1 wherein the conductive contacts are resilient spring contacts.

4. The method in accordance with claim 3 wherein step b comprises:

clamping the multiple die assembly to the substrate so that the spring contacts are compressed against the conductors on the surface of the substrate.

5. A method for fabricating and testing a multiple die assembly, the method comprising the steps of:

a. providing a substrate having conductors formed thereon;

b. providing a base IC wafer including at least one base IC die having a first surface and a second surface parallel to the first surface;

c. forming conductive contacts on the first surface of the IC die, each conductive contact having a free end extending outward from the first surface of the base die;

d. linking a first secondary IC die;

e. linking the first secondary IC die to the first surface of the base IC die through first conductive signal paths;

f. separating the base IC die from other portions of the base IC wafer; and

g. positioning the base IC die such that its first surface faces the substrate, such that free ends of the first conductive contacts contact the conductors on the substrate, and such that the first secondary IC die resides between the first surface of the base IC die and the substrate, wherein the conductive contacts convey signals between the base IC die and the conductors on the substrate.

6. The method in accordance with claim 5 wherein the conductive contacts are resilient spring contacts.

7. The method in accordance with claim 5 wherein the first conductive signal paths are formed by solder.

8. The method in accordance with claim 5, wherein step d comprises the substeps of:

d1. providing a secondary IC wafer having the secondary IC die formed thereon,

d2. testing the secondary IC die, and then

d3. cutting the secondary IC wafer to singulate the secondary IC die.

9. The method in accordance with claim 5, further comprising the step of:

n. prior to step 3, linking the base IC die through the conductive contacts to an apparatus for testing the base IC die.

10. The method in accordance with claim 5, further comprising the step of:

i. prior to step f, linking the multiple die assembly through the conductive contacts to an apparatus for testing the multiple die assembly.

11. The method in accordance with claim 9, further comprising the step of:

i. prior to step g, linking the multiple die assembly through the conductive contacts to an apparatus for testing the multiple die assembly.

12. The method in accordance with claim 5 further comprising the steps of:

h. providing a second secondary IC die;

i. linking the second secondary IC die to the second surface of the base IC die through second conductive signal paths.

13. The method in accordance with claim 12 further comprising the step of

j. forming conductive vias through the base IC wafer for providing signal paths between the first and second surfaces of the base IC die.

14. The method in accordance with claim 12 wherein the second conductive signal paths comprise spring contacts.

15. The method in accordance with claim 12 wherein solder forms the second conductive signal paths.

16. The method in accordance with claim 5 wherein the substrate is a printed circuit board substrate.

17. The method in accordance with claim 5 wherein the substrate is a semiconductor substrate.

18. The method in accordance with claim 6 wherein the first conductive signal paths are formed by solder and wherein step d comprises the substeps of:

d1. providing a secondary IC wafer having the secondary IC die formed thereon,

d2. testing the secondary IC die, and then

d3 cutting the secondary IC wafer to singulate the secondary IC die.

19. The method in accordance with claim 18 further comprising the steps of:

h. prior to step e, linking the base IC die through the spring contacts to an apparatus for testing the base IC die, and

i. prior to step f, linking the multiple die assembly through the spring contacts to an apparatus for testing the multiple die assembly.

20. The method in accordance with claim 19 further comprising the steps of:

j. providing a second secondary IC die;

k. linking the second secondary IC die to the second surface of the base IC die through second conductive signal paths, and

l. forming conductive vias through the base IC wafer for providing signal paths between the first and second surfaces of the base IC die.

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)

25. (canceled)

26. (canceled)

27. (canceled)

28. (canceled)

29. (canceled)

30. (canceled)

31. (canceled)

32. A multiple die electronic system comprising:

a substrate having conductors formed thereon,

a base IC die having a first surface facing the substrate and a second surface parallel to the first surface,

a second level IC die having a third surface and residing between the first surface of the base IC die and the substrate and linked to the first surface of the base IC die and the substrate and linked to the first surface of the base IC die through first conductive contacts for conveying signals between the base IC die and the second level IC die,

a third level IC die residing between the first surface of the base IC die and the third surface of the second level IC die and linked to the third surface of the second level IC die through conductive signal paths, and

second conductive contacts extending between the first surface of the base IC die and the conductors on the substrate for conveying signals between the base IC die and the conductors on the substrate.

33. The multiple die electronic system in accordance with claim 32 wherein solder forms the conductive signal paths.

34. The multiple die electronic system in accordance with claim 32 wherein the substrate is a printed circuit board substrate.

35. The multiple die electronic system in accordance with claim 32 wherein the substrate is a semiconductor substrate.

36. The multiple die electronic system in accordance with claim 32 wherein the first and second conductive contacts comprise resilient first and second spring contacts.

37. The multiple die electronic system in accordance with claim 36 wherein the first spring contacts are formed on the first surface of the base IC die and soldered to the third surface of the second level IC die.

38. The multiple die electronic system in accordance with claim 36 wherein the second spring contacts are formed on the first surface of the base IC die and soldered to the conductors on the substrate.