Test device for wafer testing digital semiconductor circuits

• US 20050162176A1
• Filed: 11/24/2004
• Published: 07/28/2005
• Est. Priority Date: 11/27/2003
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Bucksch, Thorsten
• Granted Patent: US 7,180,313 B2
• Time in Patent Office: Days
• US Class Current: 324/754.180
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals to/from a test head and distributes signal channels, carrying test signals, to the respective location on the wafer via an interposer. The interposer has a printed circuit board with contact pins on both sides, and a needle or contact stud card. Additionally, all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier, the signal amplifiers preferably being digital signal amplifiers which are mounted on the printed circuit board of the interposer.

Claims

1. A test device for testing digital semiconductor circuits at wafer level comprising:

an interposer comprising a printed circuit board with contact pins on both sides, and a needle or contact stud card;

a probe card which sends and receives digital test signals to and from a test head and distributes signal channels, carrying test signals, to respective locations on a wafer via the interposer;

wherein all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier.

2. The test device as claimed in claim 1, wherein signal amplifiers in the signal channels are digital signal amplifiers.

3. The test device as claimed in claim 1, wherein signal amplifiers in the signal channels are in physical proximity to the needle or contact stud card.

4. The test device as claimed in claim 1, wherein signal amplifiers in the signal channels are mounted on the printed circuit board of the interposer.

5. The test device as claimed in claim 1, wherein at least one signal amplifier amplifies a respective signal received from the wafer or transmitted to the wafer using stipulated high and low levels.

6. The test device as claimed in claim 1, wherein at least one signal amplifier amplifies a respective signal received from the wafer or transmitted to the wafer using variable high and/or low signal levels.

7. The test device as claimed in claim 6, wherein the variable signal levels can each be set or regulated from outside of the interposer.

8. The test device as claimed in claim 1, wherein the test device can be retrofit.