System including address generator and address generator

• US 20050162438A1
• Filed: 11/10/2004
• Published: 07/28/2005
• Est. Priority Date: 01/26/2004
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hosogi, Koji, Nakata, Hiroaki, Ehama, Masakazu, Tanaka, Kazuhiko, Fujii, Yukio
• Application Number:
  US10/984,974
• Publication Number:
  US 20050162438A1
• Time in Patent Office: Days
• US Class Current: 345/572
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

There are provided a system including an address generator and its address generator, capable of generating an address needed for resolution conversion or the like of display data, by using an adder and counters without using a multiplier, which is disadvantageous as regards the mounting area and operation speed when mounting the address generator on an integrated circuit. A first portion for selecting a value from a plurality of values prepared to calculate the next address and adding the selected value, and a second portion for generating a signal to control selection of the value to be added are prepared. A plurality of counters are prepared in the second portion, and the value to be added is selected based on values in these counters. This address generator is incorporated in a DMA controller, memory access controller, display controller or the like, to implement resolution conversion or the like.

Claims

1. A system including an address generator for generating an address needed at time of memory access, said address generator comprising:

an address updater for updating an address by adding an increment of the address; and

an address increment selector having a plurality of counters in which respective initial values can be set independently and a plurality of registers, each for specifying increment of said address, said address increment selector selecting the increment of the address on the basis of a value in at least one counter included in the counters.

2. A system including an address generator, according to claim 1, wherein at least one increment of the address and at least one of counter initial values are shared and retained by the same setting register.

3. A system including an address generator, according to claim 1, wherein

the counters include a first counter and a second counter, and

a value in said second counter is updated when said first counter has a specific value, and an address increment is selected by a value in said second counter when said first counter has a specific value.

4. A system including an address generator, according to claim 1, wherein

the counters comprise a first counter, a second counter and a third counter, and

values in said second counter and said third counter are updated when said first counter has a specific value, and

an address increment is selected by a value in said third counter when said first counter has a specific value.

5. A system including an address generator, according to claim 1, wherein

the counters comprise a first counter, a second counter and a third counter, and

a value in said second counter is updated when said first counter has a specific value, a value in said third counter is updated when said first counter and said second counter has specific values respectively, and an address increment is selected by a value in said second counter when said first counter has a specific value.

15. A system including an address generator, according to claim 1, wherein said system is a DMA transfer controller for conducting data transfer between a memory and a memory or between a memory and an I/O.

16. A system including an address generator, according to claim 1, wherein said system is a display controller for generating a signal to be output to a display device.

17. A system including an address generator, according to claim 1, comprising:

a memory controller for controlling memory access;

a display controller for generating a signal to be output to a display device; and

a data path for directly transferring display data from said memory controller to said display controller,

wherein said memory controller comprises said address generator.

18. A system including an address generator, according to claim 1, comprising:

a memory controller for controlling memory access;

a DMA controller capable of conducting data transfer between a memory and an I/O; and

a display controller for generating a signal to be output to a display device,

wherein said display controller can receive display data from said DMA controller, and said DMA controller comprises said address generator.

19. A system including an address generator, according to claim 1, comprising:

a memory controller for controlling memory access;

a DMA controller capable of conducting data transfer between a memory and a memory; and

a processor for conducting computation processing,

wherein said processor has an accessible internal memory, said DMA controller can access said internal memory as well, and said DMA controller comprises said address generator.

6. A system including an address generator for generating an address needed at time of memory access, said address generator comprising:

a start address register for specifying a start address;

a first counter;

a first initial value register for specifying a count period of said first counter;

a second counter for counting every count period of said first counter;

a second initial value register for specifying an initial value of said second counter;

a first step register for specifying an increment of the address when said first counter has a value different from a specific value; and

a second step register and a third step register selected on the basis of a value in said second counter to specify the increment of the address when said first counter has a specific value and said second counter has a value different from a specific value.

7. A system including an address generator, according to claim 6, comprising an address generator that has said first initial value register for specifying a count period of said first counter and said second step register or said third step register as one register.

8. A system including an address generator, according to claim 6, comprising an address generator that uses a fixed value as a substitute for said first step register.

9. A system including an address generator for generating an address needed at time of memory access, said address generator comprising:

a start address register for specifying a start address;

a first counter;

a first initial value register for specifying a count period of said first counter;

a second counter for counting every count period of said first counter;

a second initial value register for specifying an initial value of said second counter;

a third counter for counting every count period of said first counter;

a third initial value register for specifying an initial value of said third counter;

a first step register for specifying an increment of the address to be used when said first counter has a value different from a specific value;

a second step register for specifying the increment of the address to be used when said first counter has a specific value and said third counter has a specific value; and

a third step register for specifying the increment of the address to be used when said first counter has a specific value and said third counter has a value different from a specific value.

10. A system including an address generator, according to claim 9, comprising an address generator that has said first initial value register for specifying a count period of said first counter and said second step register or said third step register as one register.

11. A system including an address generator, according to claim 9, comprising an address generator that uses a fixed value as a substitute for said first step register.

12. A system including an address generator for generating an address needed at time of memory access, said address generator comprising:

a start address register for specifying a start address;

a first counter;

a first initial value register for specifying a count period of said first counter;

a second counter for counting every count period of said first counter;

a second initial value register for specifying an initial value of said second counter;

a third counter for counting every count period of said second counter;

a third initial value register for specifying an initial value of said third counter;

a first step register for specifying an increment of the address to be used when said first counter has a value different from a specific value;

a second step register for specifying the increment of the address to be used when said first counter has a specific value and said second counter has a specific value; and

a third step register for specifying the increment of the address to be used when said first counter has a specific value and said second counter has a value different from a specific value.

13. A system including an address generator, according to claim 12, comprising an address generator that has said first initial value register for specifying a count period of said first counter and said second step register or said third step register as one register.

14. A system including an address generator, according to claim 12, comprising an address generator that uses a fixed value as a substitute for said first step register.

20. An address generator for generating an address needed at time of memory access, said address generator comprising:

an address updater for updating an address by adding an increment of the address; and

an address increment selector having a plurality of counters in which respective initial values can be set independently, said address increment selector selecting the increment of the address on the basis of values in the counters.