Systems and methods that employ inductive current steering for digital logic circuits

• US 20050162797A1
• Filed: 01/28/2004
• Published: 07/28/2005
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Notthoff, Johannes K.
• Granted Patent: US 7,057,971 B2
• Time in Patent Office: Days
• US Class Current: 361/100
• CPC Class Codes: H03K 17/04113 in bipolar transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration

Abstract

The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is “on” while the other is “off,” which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters. Further, the systems and methods can be utilized to construct flip-flops and shift registers by coupling differential transistor pairs and driving these pairs with the transformer-based single-ended or differential clock.

Claims

1. A switching system that employs inductive current steering, comprising:

at least two elements that provide respective inductive currents;

a steering component that directs the inductive currents to a switching component; and

a differential component associated with the switching component that employs the inductive currents to generate a differential output.

2. The system of claim 1, the at least two elements are transformers.

3. The system of claim 1, respective primary windings of the at least two elements are powered by a differential clock bus.

4. The system of claim 1, respective secondary windings of the at least two elements generate the inductive currents in connection with applying a differential signal across the at least two elements.

5. The system of claim 1, the inductive currents are 180 degrees out-of-phase.

6. The system of claim 1, one of the inductive currents is utilized to turn “

on”

a first switch of the differential component and the other inductive current is utilized to turn “

off”

a second switch of the differential component.

7. The system of claim 1, a differential clock bus is utilized to toggle the state of a first switch and a second switch of the differential component.

8. The system of claim 1, the differential component comprises at least one differential transistor pair.

9. The system of claim 8, the differential transistor pair comprises at least two of an Indium Phosphide (InP), a carbon-doped InP, an Indium Gallium Arsenide (InGaAs), a GaAs, an Aluminum Gallium Arsenide (AlGaAs) heterojunction bipolar transistor (HBT), a Silicon-Germanium (SiGe) bipolar transistor (BJT) add Field Effect Transistor (FET).

10. The system of claim 1 is employed in one or more of a register, a flip-flop, a frequency divider, a memory module, a latch, a multiplexer, an oscillator, a power amplifier, an RF integrated circuit, and an ASIC.

11. The system of claim 1, the differential output is employed to drive a logic gate.

12. A switching system that utilizes inductive current steering, comprising:

a current steering component that generates activating and deactivating signals; and

a switching component that receives the activating and deactivating signals and generates a differential output based on the activating and deactivating signals.

13. The system of claim 12, the current steering component comprises a transformer.

14. The system of claim 12, a primary winding associated with the current steering component is energized by a signal from a single clock bus, the energized primary winding induces a current in a secondary winding that is associated with the current steering component.

15. The system of claim 12, a secondary winding associated with the current steering component is center-tapped, the center tap is coupled to a current source, and a first and a second end of the secondary winding provide the activating and deactivating signals to the switching component.

16. The system of claim 12, the activating and deactivating signals are 180 degrees out-of-phase.

17. The system of claim 12, the activating signal facilitates generating a high output and the deactivating signal facilitates generating an opposite polarity low output of the differential output.

18. The system of claim 12, the switching component comprises a differential transistor pair.

19. The system of claim 12 is employed in one or more of a register, a flip-flop, a frequency divider, a memory module, a latch, a multiplexer, an oscillator, a power amplifier, an RF integrated circuit, and an ASIC.

20. A data track and hold system that employs inductive current switching, comprising:

at least two data latches; and

a transformer based clock bus that controls the at least two data latches via inductive current.

21. The system of claim 20, respective data latches comprise a track differential transistor pair and a hold differential transistor pair.

22. The system of claim 20, the transformer based clock bus comprises at least one transformer for each respective transistor of the at least two data latches, respective transformers provide inductive current to respective transistors, and the inductive current defines the state of the respective transistors.

23. The system of claim 20 is employed as a D-flip-flop.

24. A shift register that employs inductive current switching, comprising:

a plurality of flip-flops; and

a clock bus that induces current, which defines state of respective flip-flops.

25. The system of claim 24, the plurality of flip-flops is serially coupled via routing at least one output of one flip-flop to at least one input of a succeeding flip-flop.

26. The system of claim 24, at least one flip-flop is configured with a fanout of one.

27. The system of claim 24, the clock bus comprises at least one transformer that generates the induced current.

28. A method for steering inductive current through one or more differential transistor pairs, comprising:

receiving a clock signal;

conveying the clock signal through on or more transformers to generate one or more inductive currents; and

providing the one or more inductive currents to the one or more differential transistor pairs.

29. The method of claim 28, the clock signal is conveyed over one of a single clock bus and a differential clock bus.

30. The method of claim 28, the one or more inductive currents comprise at least two currents that are 180 degrees out of phase with respect to one another.

31. The method of claim 28, the one or more inductive currents can be toggled via the clock signal in order to toggle the state of the one or more differential transistor pairs.

32. A inductive current-based data latching method, comprising:

coupling at least two data latches in series;

employing a transformer based clock bus that induces current; and

routing the induced current to the at least two data latches to track and hold data within the data latches.

33. The method of claim 32 is employed in connection with one or more of a register, a flip-flop, a frequency divider, a memory module, a latch, a multiplexer, an oscillator, a power amplifier, an RF integrated circuit, and an ASIC.

34. A system that provides inductive current to a differential transistor pair, comprising:

means for receiving a clock signal;

means for generating an inductive current based on the clock signal; and

means for steering the inductive current through the differential transistor pair in order to effectuate the output state of the differential transistor pair.