Method of reading NAND memory to compensate for coupling between storage elements

• US 20050162913A1
• Filed: 01/26/2004
• Published: 07/28/2005
• Est. Priority Date: 01/26/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian
• Granted Patent: US 7,372,730 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for reading non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent word line written after word line; and reading the selected bit in word line by selectively adjusting at least one read parameter. In one embodiment, the read parameter is the sense voltage. In another embodiment, the read parameter is the pre-charge voltage. In yet another embodiment, both the sense and the pre-charge voltage are adjusted.

Claims

1. A method for reading non-volatile memory arranged in columns and rows, comprising the steps of:

selecting a word-line WLn to be read;

reading an adjacent word line (WLn+1) written after word line WLn; and

reading the selected bit in word line WLn by selectively adjusting at least one read parameter.

2. The method of claim 1 wherein the read parameter is the sense voltage.

3. The method of claim 2 wherein the step of reading the bit includes increasing the sense voltage.

4. The method of claim 3 wherein the step of increasing the sense voltage includes increasing the sense voltage by an amount equal to a fraction of the maximum coupling effect of the adjacent bit on the selected bit.

5. The method of claim 4 wherein the fraction is one-half.

6. The method of claim 1 wherein the read parameter is the pre-charge voltage.

7. The method of claim 1 wherein the step of reading the bit includes decreasing the pre-charge voltage.

8. The method of claim 7 wherein the step of decreasing the pre-charge voltage includes decreasing the sense voltage by an amount equal to a fraction of the maximum coupling effect of the adjacent bit on the selected bit.

9. The method of claim 1 wherein the method includes the step, following the step of reading an adjacent word line, of determining whether a bit in word line WLn+1 adjacent to the selected bit has a threshold voltage above a check voltage.

10. The method of claim 9 wherein said step of reading the selected bit occurs only if said bit in word line WLn+l is greater than the check voltage.

11. The method of claim 10 wherein the check voltage is one half of the voltage threshold distribution.

12. The method of claim 1 wherein the bits hold a multi-state memory, the step of reading an adjacent word line includes determining the threshold voltage state of the bit.

13. The method of claim 12 wherein the step of reading includes reading the bit at least three times.

14. The method of claim 13 wherein the step of reading the selected bit includes decreasing the sense voltage by an amount equal to the coupling effect of the adjacent bit on the selected bit.

15. The method of claim 13 wherein the step of reading the selected bit includes increasing the pre-charge voltage by an amount equal to the coupling effect of the adjacent bit on the selected bit.

16. The method of claim 1 wherein said at least one read parameter includes both the pre-charge voltage and the sense voltage.

17. A method for reading non-volatile memory arranged in columns and rows, comprising the steps of:

determining a selected bit to be read in a first word-line;

reading an adjacent word line written after the first word line;

determining whether a bit adjacent to the selected bit has a threshold voltage greater than a check value; and

if the selected bit has a threshold voltage greater than the check value, reading the selected bit in word line by selectively adjusting at least one read parameter.

18. The method of claim 17 wherein the read parameter is the sense voltage.

19. The method of claim 18 wherein the step of reading the bit includes increasing the sense voltage.

20. The method of claim 19 wherein the step of increasing the sense voltage includes increasing the sense voltage by an amount equal to one-half of the maximum coupling effect of the adjacent bit on the selected bit.

21. The method of claim 17 wherein the read parameter is th pre-charge voltage.

22. The method of claim 17 wherein the step of reading the bit includes decreasing the pre-charge voltage.

23. The method of claim 22 wherein the step of decreasing the pre-charge voltage includes decreasing the sense voltage by an amount equal to one-half of the maximum coupling effect of the adjacent bit on the selected bit.

24. The method of claim 17 wherein the check voltage is one half of the voltage threshold distribution of a multi-state cell array.

25. A memory system including code enabling reading data from the system, comprising:

an array of multi-state memory cells arranged in rows and columns;

a controller executing said code, the code performing the steps of;

determining a selected bit to be read in a first row-line;

reading an adjacent row line written after the first row line;

determining whether a bit adjacent to the selected bit has a threshold voltage greater than a check value; and

if the selected bit has a threshold voltage greater than the check value, reading the selected bit in row line by selectively adjusting at least one read parameter.

26. The method of claim 25 wherein the read parameter is the sense voltage.

27. The method of claim 26 wherein the step of reading the bit includes increasing the sense voltage.

28. The method of claim 25 wherein the read parameter is the pre-charge voltage.

29. The method of claim 25 wherein the step of reading the bit includes decreasing the pre-charge voltage.

30. The method of claim 25 wherein the step of reading includes adjusting both the pre-charge voltage and the sense voltage.

31. The method of claim 25 wherein the check voltage is one half of the voltage threshold distribution of a multi-state cell array.

32. An apparatus, comprising:

means for determining a selected bit to be read in a first word-line;

means for reading an adjacent word line written after the first word line;

means for determining whether a bit adjacent to the selected bit has a threshold voltage greater than a check value; and

means for reading the selected bit in word line by selectively adjusting at least one read parameter if the selected bit has a threshold voltage greater than the check value.