Providing memory test patterns for DLL calibration
First Claim
1. A method of providing a signaling pattern for a bus having a plurality of bit lines, said method comprising:
- for each selected bit line in said plurality of bit lines;
selecting at least one of a plurality of signals to be sent over said selected bit line; and
further selecting at least one of said plurality of signals to be sent over at least one bit line in said plurality of bit lines other than said selected bit line.
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Accused Products
Abstract
A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial presence detect (SPD) circuit memory. The test bits stored in the SPD memory are transferred to a memory controller register (MCR) and implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.
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Citations
25 Claims
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1. A method of providing a signaling pattern for a bus having a plurality of bit lines, said method comprising:
for each selected bit line in said plurality of bit lines;
selecting at least one of a plurality of signals to be sent over said selected bit line; and
further selecting at least one of said plurality of signals to be sent over at least one bit line in said plurality of bit lines other than said selected bit line. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of signaling a bus having a plurality of bit lines, said method comprising:
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transmitting one of a plurality of signals on a selected one of said plurality of bit lines;
simultaneously transmitting one of said plurality of signals on one or more of said plurality of bit lines other than said selected bit line; and
repeating said transmitting and simultaneously transmitting for each bit line in said plurality of bit lines. - View Dependent Claims (8, 9)
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10. A method of operating a memory connected to a bus, said method comprising:
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transmitting one of a plurality of signals on a selected one of a plurality of bit lines in said bus;
simultaneously transmitting one of said plurality of signals on one or more of said plurality of bit lines other than said selected bit line; and
performing a data write/read operation at a data storage location in said memory using said bus while said signals in said transmitting and simultaneously transmitting are present on respective bit lines in said bus. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A system comprising:
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a plurality of memory cells to store data;
a serial presence detect circuit containing a plurality of test bits;
a bus having a plurality of bit lines; and
a memory controller in communication with said plurality of memory cells and said serial presence detect circuit via said bus, wherein said memory controller is configured to;
store therein said plurality of test bits received from said serial presence detect circuit via said bus, transmit a first one of said plurality of test bits on a selected one of said plurality of bit lines in said bus, also transmit a second one of said plurality of test bits on one or more of said plurality of bit lines other than said selected bit line, and facilitate a data write/read operation at one of said plurality of memory cells using said bus while said first one and said second one of said plurality of test bits are present on respective bit lines in said bus. - View Dependent Claims (17, 18, 19)
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20. A system comprising:
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a memory chip having a serial presence detect circuit containing a plurality of test bits;
a bus having a plurality of bit lines; and
a processor connected to said memory chip via said bus and in communication therewith through said bus, wherein said processor includes;
a memory controller configured to perform the following;
store therein said plurality of test bits received from said serial presence detect circuit via said bus, transmit a first one of said plurality of test bits on a selected one of said plurality of bit lines in said bus, and further transmit a second one of said plurality of test bits on one or more of said plurality of bit lines other than said selected bit line. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification