Selective epitaxy vertical integrated circuit components and methods

• US 20050164454A1
• Filed: 01/27/2004
• Published: 07/28/2005
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Leslie, Terrence C.
• Granted Patent: US 7,372,091 B2
• Time in Patent Office: Days
• US Class Current: 438/269
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. These components are grown directly in electrical communication lines. Moreover, these components are adapted for use in memory devices and are believed to not require the use of shallow trench isolation.

Claims

1. A memory cell, comprising:

a vertical access device including a selective epitaxy mesa; and

a storage device on the selective epitaxy mesa.

2. The memory cell of claim 1, wherein selective epitaxy mesa includes a bottom source/drain and a top source/drain, and wherein the selective epitaxy mesa further includes a conductive body separating the bottom source/drain from the top source/drain.

3. The memory cell of claim 2, wherein the bottom source/drain is an in situ doped region.

4. The memory cell of claim 2, wherein the top source/drain is an in situ doped region.

5. The memory cell of claim 2, wherein the bottom source/drain includes a semi-annular ring around a bottom portion of the selective epitaxy mesa.

6. The memory cell of claim 5, wherein the vertical access device includes a signal line having a first height, and wherein the bottom source/drain includes a second height that is about equal to the first height.

7. The memory cell of claim 5, wherein the bottom source/drain is formed by out diffusion from an adjacent conductor.

8. The memory cell of claim 1, wherein the access device is free from a shallow trench isolation layer.

9. A vertical memory cell, comprising:

a substrate;

an access device including a selective epitaxy mesa formed on and extending outwardly from the substrate; and

a storage device on the selective epitaxy mesa.

10. The memory cell of claim 9, wherein the substrate includes silicon, and wherein the selective epitaxy mesa includes silicon.

11. The memory cell of claim 9, wherein the access device includes a body, a first source/drain, a gate and a second source/drain, wherein the body extends between the first source/drain and the second source/drain, and wherein the first source/drain and the second source/drain are each a selective epitaxy doped region of the selective epitaxy mesa.

12. The memory cell of claim 11, wherein the first source/drain region extends horizontally around the selective epitaxy mesa.

13. The memory cell of claim 12, wherein the first source/drain region is adapted to contact a bit line.

14. The memory cell of claim 12, wherein the second source/drain region is spaced from the substrate by the body.

15. The memory cell of claim 14, wherein the second source/drain region is an in situ N+ doped region of the selective epitaxy mesa.

16. A vertical memory cell, comprising:

a substrate;

an electrical signal line on the substrate;

an access device including a selective epitaxy mesa formed on and extending outwardly from the substrate, the selective epitaxy mesa including a first source/drain region adjacent the substrate and in electrically communication with the electrical signal line; and

a storage device on the selective epitaxy mesa.

17. The vertical memory cell of claim 16, wherein the electrical signal line has a first height, and wherein the first source/drain region has a second height equal to or less than the first height.

18. The vertical memory cell of claim 16, wherein the selective epitaxy mesa cantilevers upwardly from the substrate, and wherein the selective epitaxy mesa includes an end, remote from the substrate, forming a second source/drain region.

19. The vertical memory cell of claim 16, wherein the first source/drain region extends around an outer periphery of the selective epitaxy mesa.

20. The vertical memory cell of claim 19, wherein the electrical signal line extends around the first source/drain region.

21. The vertical memory cell of claim 16, wherein the first source/drain region extends partially around an outer periphery of the selective epitaxy mesa.

22. The vertical memory cell of claim 21, wherein the electrical signal line extends around the first source/drain region.

23. The vertical memory cell of claim 21, wherein the electrical signal line partially around the selective epitaxy mesa.

24. The vertical memory cell of claim 16, wherein the first source/drain region is adapted to electrically communicate with a column address decoder through a buried bit line.

25. The vertical memory cell of claim 24, wherein the second source/drain region is adapted to electrically communicate with the storage device.

26. A vertical memory cell, comprising:

a substrate;

an electrical signal line on the substrate;

an access device including a selective epitaxy mesa formed on and extending outwardly from the substrate, the selective epitaxy mesa including a first source/drain region adjacent the substrate and in electrically communication with the electrical signal line, the selective epitaxy mesa further including a body extending vertically from the first source/drain region, an insulator on the body, and a gate on the insulator; and

a storage device on the selective epitaxy mesa remote from the substrate.

27. The vertical memory cell of claim 26, wherein the insulator surrounds the body, and wherein the gate surrounds the insulator such that the gate effects electrical conductivity of the body from more than one angle.

28. The vertical memory cell of claim 26, wherein the insulator surrounds the body, and wherein the gate partially overlies the insulator such that the gate effects electrical conductivity of the body from more than one angle.

29. The vertical memory cell of claim 28, wherein the gate overlies over half of a surface area of the body.

30. The vertical memory cell of claim 26, wherein the electrical signal line includes titanium.

31. A vertical transistor, comprising:

a vertical, selective epitaxy body extending from a horizontal substrate;

a first doped region in the body adjacent the substrate;

a second doped region in the body remote from the substrate;

an undoped intermediate region between the first doped region and the second doped region; and

a gate at least partially surrounding the intermediate region.

32. The transistor of claim 31, wherein the body is adapted to form a channel between the doped first region and the doped second region.

33. The transistor of claim 31, wherein the first doped region is adapted to be in electrically communication with a buried bit line.

34. The transistor of claim 31, wherein the gate is adapted to be in electrical communication with a word line.

35. The transistor of claim 31, wherein the gate overlies at least half of the surface area of the intermediate region.

36. The transistor of claim 31, wherein the gate overlies at least about 75% of the surface area of the intermediate region.

37. The transistor of claim 31, wherein the gate overlies about all of the surface area of the intermediate region.

38. The transistor of claim 31, wherein the vertical, selective epitaxy body is generally cylindrical.

39. The transistor of claim 38, wherein the gate is generally annular and extends completely around the body.

40. The transistor of claim 38, wherein the first doped region is cylindrical.

41-70. -70. (canceled)