Zirconium oxide and hafnium oxide etching using halogen containing chemicals

• US 20050164479A1
• Filed: 01/27/2004
• Published: 07/28/2005
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Peng-Fu, Chiu, Yuan-Hung, Perng, Baw-Ching, Sung, Mei-Hui
• Granted Patent: US 7,012,027 B2
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₈, C₄F₆, C₅F₆, BCl₃, Br₂, HF, HCl, HBr, HI, and NF₃ and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

Claims

1. A method of removing a high k dielectric layer from a substrate comprising the steps of:

(a) providing a substrate with isolation regions and an active area between said isolation regions;

(b) depositing a high k dielectric layer on said substrate;

(c) forming a patterned gate electrode on said high k dielectric layer; and

(d) anisotropically etching through exposed portions of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases.

2. The method of claim 1 further comprised of forming an interfacial layer on said substrate prior to depositing said high k dielectric layer.

3. The method of claim 2 wherein the interfacial layer is comprised of silicon oxide, silicon nitride, or silicon oxynitride with a thickness between about 1 and 30 Angstroms.

4. The method of claim 1 wherein said high k dielectric layer has a thickness from about 10 to 120 Angstroms and is comprised of ZrO₂, HfO₂, Ta₂O₅, TiO₂, Al₂O₃, Y₂O₃ La₂O₅ or is a silicate, nitride, or oxynitride of one or more of Zr, Hf, Ta, Ti, Al, Y, and La.

5. The method of claim 1 wherein said high k dielectric layer is formed by an atomic layer deposition (ALD), chemical vapor deposition (CVD) or metal organic CVD (MOCVD) technique.

6. The method of claim 1 wherein said high k dielectric layer is comprised of ZrO₂ or HfO₂ and includes one of Ta₂O₅, TiO₂, Al₂O₃, Y₂O₃ and La₂O₅ as a minor component.

7. The method of claim 1 wherein said one or more halogen containing gases comprises CF₄, CHF₃, CH₂F₂, BCl₃, Br₂, HF, HCl, HBr, HI, NF₃ and mixtures thereof.

8. The method of claim 1 wherein step (d) is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, a chamber pressure from about 4 to 80 mTorr, a RF power between about 200 and 1000 Watts, a bias power from about 20 to 500 Watts at a temperature between 20°

C. and 200°

C. for a period of about 5 to 200 seconds.

9. The method of claim 8 further comprised of adding one or more inert gases including Ar, Xe, He, and N₂ having a flow rate between about 10 and 250 sccm.

10. The method of claim 8 further comprised of adding one or more of O₂, CO, CO₂, and N₂O as an oxidant gas having a flow rate between about 10 and 300 sccm.

11. The method of claim 9 further comprised of adding one or more of O₂, CO, CO₂, and N₂O as an oxidant gas having a flow rate between about 10 and 300 sccm.

12. The method of claim 10 wherein a high k dielectric layer comprising HfO₂ is etched by a method that includes a CF₄ flow rate of about 30 sccm, a CH₃F flow rate of about 60 sccm, an O₂ flow rate of about 10 sccm, a 5 mTorr chamber pressure, a RF power of about 600 Watts and a bias power of about 200 Watts for a period of about 10 seconds.

13. The method of claim 11 wherein a high k dielectric layer comprising HfO₂ is etched by a method that includes a CF₄ flow rate of about 5 sccm, an O₂ flow rate of about 200 sccm, an Ar flow rate of about 100 sccm with a chamber pressure of 20 mTorr, a RF power of about 600 Watts, and a bias power of about 100 Watts for a period of about 23 seconds to end point plus an overetch period for about an additional 23 seconds beyond end point.

14. The method of claim 1 wherein the substrate is silicon and the isolation regions are comprised of silicon oxide and the etch rate of said high k dielectric layer in step (d) is more than twice the rate of etching silicon oxide or silicon.

15. A method of forming a semiconductor device comprising:

(a) depositing a high k dielectric layer on a substrate;

(b) forming a patterned photoresist layer on said high k dielectric layer which exposes portions of the high k dielectric layer;

(c) anisotropically etching through exposed portions of said high k dielectric layer with a plasma etch comprising a halogen containing gas to form a pattern in the high k dielectric layer;

(d) removing said photoresist;

(e) etch transferring said pattern in said high k dielectric layer into said substrate; and

(f) removing said high k dielectric layer with a plasma etch comprising a halogen containing gas.

16. The method of claim 15 wherein said high k dielectric layer has a thickness from about 10 to 120 and is comprised of ZrO₂, HfO₂, Ta₂O₅, TiO₂, Al₂O₃, Y₂O₃, La₂O₅ or is a silicate, nitride, or oxynitride of one or more of Zr, Hf, Ta, Ti, Al, Y, and La.

17. The method of claim 15 wherein said high k dielectric layer is formed by an ALD, CVD, or MOCVD technique.

18. The method of claim 15 wherein said anisotropic etching with halogen containing gases includes CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₈, C₄F₆, C₅F₆, BCl₃, Br₂, HF, HCl, HBr, HI, and NF₃ and mixtures thereof.

19. The method of claim 15 wherein step (c) is performed in an etch chamber with a process comprising a halogen containing gas flow rate between 2 and 200 sccm, a chamber pressure from about 4 to 80 mTorr, a RF power between about 200 and 3000 Watts, a bias power from 0 to about 2000 Watts, and a chamber temperature between 20°

C. and 200°

C. for a period of from about 20 to 300 seconds.

20. The method of claim 19 further comprised of the addition of one or more inert gases including Ar, Xe, He, and N₂ having a flow rate between about 10 and 300 sccm.

21. The method of claim 15 wherein an etch chemistry is chosen for step (e) that selectively etches said substrate at a rate of more than about 3 times faster than said high k dielectric layer.

22. The method of claim 15 wherein the high k dielectric layer is removed after etching said substrate by a process comprising one or more halogen containing gases including CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₈, C₄F₆, C₅F₆, BCl₃, Br₂, HF, HCl, HBr, HI, and NF₃ and one or more oxidant gases including CO, O₂, CO₂, and N₂O.

23. The method of claim 22 wherein the high k dielectric layer is removed by a process comprising a CF₄ flow rate of about 30 sccm, a CH₃F flow rate of about 60 sccm, an O₂ flow rate of about 10 sccm with a 5 mTorr chamber pressure, a RF power of about 600 Watts and a bias power of about 200 Watts.

24. The method of claim 15 wherein step (f) is further comprised of adding one or more inert gases including Ar, Xe, He, and N₂, and one or more oxidant gases including CO, O₂, CO₂, and N₂O each having a flow rate between about 10 and 300 sccm.

25. The method of claim 24 wherein the high k dielectric layer is removed by a process comprising a CF₄ flow rate of about 5 sccm, an O₂ flow rate of about 200 sccm, an Ar flow rate of about 100 sccm with a chamber pressure of 20 mTorr, a RF power of about 600 Watts, and a bias power of about 100 Watts.

26. A method of forming a capacitor, comprising:

(a) providing a substrate with an interlevel dielectric (ILD) layer formed thereon;

(b) forming a pattern comprised of an opening with sidewalls and a bottom in said ILD layer;

(c) forming a first conducting layer on the sidewalls and bottom of said opening;

(d) forming a high k dielectric layer on the ILD layer and on the first conducting layer;

(e) forming a second conducting layer on said high k dielectric layer; and

(f) selectively removing the high k dielectric layer from above portions of the ILD layer with a plasma etch that includes one or more halogen containing gases.

27. The method of claim 26 further comprised of forming a photoresist pattern to expose portions of said second conducting layer and selectively removing said exposed portions of the second conducting layer prior to step (f).

28. The method of claim 26 wherein said high k dielectric layer is comprised of ZrO₂, HfO₂, Ta₂O₅, TiO₂, Al₂O₃, Y₂O₃, La₂O₅ or BaTiO₃.

29. The method of claim 26 wherein said high k dielectric layer is a composite layer comprised of a nitride, silicate, or oxynitride of one or more of Ta, Ti, Al, Zr, Hf, Y, or La.

30. The method of claim 26 further comprised of forming silicon nitride spacers on the sidewalls of said opening prior to step (c).

31. The method of claim 26 wherein said ILD layer is comprised of silicon oxide or BPSG.

32. The method of claim 26 wherein step (f) is performed in an etch chamber with a process comprising a halogen containing gas flow rate between 2 and 200 sccm, a chamber pressure from about 4 to 80 mTorr, a RF power between about 200 and 3000 Watts, a bias power from 0 to about 2000 Watts, and a chamber temperature between 20°

C. and 200°

C. for a period of from about 20 to 300 seconds.

33. The method of claim 26 wherein said one or more halogen containing gases comprises one or more of CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₈, C₄F₆, C₅F₆, BCl₃, Br₂, HF, HCl, HBr, HI, and NF₃.

34. The method of claim 26 wherein said plasma etch that comprises one or more halogen containing gases is further comprised of one or more inert gases including Ar, Xe, He, and N₂ having a flow rate between about 10 and 300 sccm.

35. The method of claim 26 wherein said plasma etch that comprises one or more halogen containing gases is further comprised of one or more oxidant gases including O₂, CO, CO₂, and N₂O having a flow rate between about 10 and 300 sccm.

36. The method of claim 34 further comprised of one or more oxidant gases including O₂, CO, CO₂, and N₂O having a flow rate between about 10 and 300 sccm.

37. The method of claim 26 wherein the first conducting layer is comprised of Pt, Cu, silicon, polysilicon, TiN, TaN, or SiGe.

38. The method of claim 26 wherein the second conducting layer is comprised of Pt, silicon, polysilicon, TiN, TaN, or SiGe.

39. A method comprising:

providing a substrate;

depositing a high k dielectric layer above said substrate;

forming a patterned layer above said high k dielectric layer; and

selectively etching exposed portions of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases.

40. The method of claim 39, including:

configuring said substrate to have isolation regions, and an active area between said isolation regions;

configuring said patterned layer to be a patterned gate electrode on said high k dielectric layer; and

carrying out said selectively etching in a manner that includes anisotropically etching through said high k dielectric layer with said plasma etch.

41. The method of claim 39, including:

configuring said patterned layer to be a patterned photoresist layer;

carrying out said selectively etching in a manner that includes anisotropically etching through said high k dielectric layer with said plasma etch;

removing said photoresist;

etch transferring said pattern in said high k dielectric layer into said substrate; and

removing said high k dielectric layer with a plasma etch comprising a halogen containing gas.

42. The method of claim 39, including:

providing an interlevel dielectric (ILD) layer over said substrate before said depositing of said high k dielectric layer;

forming in said ILD layer a pattern that includes an opening with sidewalls and a bottom;

forming a first conducting layer on the sidewalls of said opening;

thereafter carrying out said depositing of said high k dielectric layer to form said high k dielectric layer on the first conducting layer;

forming a second conducting layer on said high k dielectric layer.