Low-noise differential bias circuit and differential signal processing apparatus

• US 20050164649A1
• Filed: 01/21/2005
• Published: 07/28/2005
• Est. Priority Date: 01/23/2004
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakatani, Toshifumi, Itoh, Jyunji, Osako, Shinichi
• Granted Patent: US 7,324,791 B2
• Time in Patent Office: Days
• US Class Current: 455/84
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 1/3276 using the nonlinearity inherent to components, e.g. a diode
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/2823 using two active transistor of the same conductivity type H03K3/2821 takes precedence

Abstract

A low-noise differential bias circuit is provided which obtains excellent noise characteristics while ensuring excellent distortion characteristics. A collector of a transistor Q11 is connected to a voltage supply point (Vcc) via a resistor R15. A base of the transistor Q11 is connected to a base of a transistor Q1 via resistors R13, R11 connected in series. A connection point between the resistors R11, R13 is connected to the collector of the transistor Q11. A collector of a transistor Q12 is connected to the voltage supply point at connection point A via a resistor R16. A base of the transistor Q12 is connected to a base of a transistor Q2 via resistors R14, R12 connected in series. A connection point between the resistors R12, R14 is connected to the collector of the transistor Q12. By this configuration, a high frequency ground is performed at the connection point A.

Claims

1. A low-noise differential bias circuit for supplying a low-noise bias current to bases or gates of a pair of differential transistors, the low-noise differential bias circuit comprising:

a first resistor having a first end being connected to a base or gate of one of the pair of differential transistors;

a second resistor having a first end being connected to a base or gate of the other one of the pair of differential transistors;

a third resistor having a first end being connected to a second end of the first resistor;

a fourth resistor having a first end being connected to a second end of the second resistor;

a first transistor, a second end of the third resistor being connected to a base or gate of the first transistor; and

a second transistor, a second end of the fourth resistor being connected to a base or gate of the second transistor, wherein

a direct-current voltage is supplied to a connection point between the first resistor and the third resistor, a connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor, from a voltage supply point through a ground element.

2. The low-noise differential bias circuit according to claim 1, wherein the ground element includes:

a fifth resistor connecting the connection point between the first resistor and the third resistor and the collector or drain of the first transistor to the voltage supply point; and

a sixth resistor connecting the connection point between the second resistor and the fourth resistor and the collector or drain of the second transistor to the voltage supply point.

3. The low-noise differential bias circuit according to claim 1, wherein the ground element includes:

a fifth resistor connecting the collector or drain of the first transistor to the voltage supply point;

a sixth resistor connecting the collector or drain of the second transistor to the voltage supply point;

a third transistor, a base or gate of the third transistor being connected to the collector or drain of the first transistor, and an emitter or source of the third transistor being connected to the connection point between the first resistor and the third resistor;

a fourth transistor, a base or gate of the fourth transistor being connected to the collector or drain of the second transistor, and an emitter or source of the fourth transistor being connected to the connection point between the second resistor and the fourth resistor;

a first capacitor connecting the collector or drain of the first transistor to an emitter or source of the first transistor; and

a second capacitor connecting the collector or drain of the second transistor to an emitter or source of the second transistor.

4. The low-noise differential bias circuit according to claim 1, wherein the ground element includes:

a fifth resistor connecting the collector or drain of the first transistor and the collector or drain of the second transistor to the voltage supply point;

a third transistor, a base or gate of the third transistor being connected to the collector or drain of the first transistor, and an emitter or source of the third transistor being connected to the connection point between the first resistor and the third resistor; and

a fourth transistor, a base or gate of the fourth transistor being connected to the collector or drain of the second transistor, and an emitter or source of the fourth transistor being connected to the connection point between the second resistor and the fourth resistor.

5. The low-noise differential bias circuit according to claim 1, wherein the first and second transistors are selected from the group consisting of an NPN bipolar transistor and an N-channel MOS field-effect transistor.

6. The low-noise differential bias circuit according to claim 5, wherein an emitter or source of each of the first and second transistors is grounded.

7. The low-noise differential bias circuit according to claim 5, wherein an emitter or source of each of the first and second transistors is grounded through a resistor.

8. The low-noise differential bias circuit according to claim 5, wherein an emitter or source of each of the first and second transistors is grounded through an inductor.

9. The low-noise differential bias circuit according to claim 1, wherein the first and second transistors are selected from the group consisting of a PNP bipolar transistor and a P-channel MOS field-effect transistor.

10. The low-noise differential bias circuit according to claim 9, wherein an emitter or source of each of the first and second transistors is connected to the voltage supply point.

11. The low-noise differential bias circuit according to claim 9, wherein an emitter or source of each of the first and second transistors is connected to the voltage supply point via a resistor.

12. The low-noise differential bias circuit according to claim 9, wherein an emitter or source of each of the first and second transistors is connected to the voltage supply point via an inductor.

13. The low-noise differential bias circuit according to claim 1, wherein a connection from the ground element to the voltage supply point or a ground point is established by a signal wire.

45. A doubler using the low-noise differential bias circuit of claim 1.

14. A differential signal processing apparatus comprising a low-noise differential bias circuit for generating a low-noise bias current;

and a differential signal processing circuit for performing predetermined differential signal processing, wherein the low-noise differential bias circuit includes;

a first resistor;

a second resistor;

a third resistor having a first end being connected to a first end of the first resistor;

a fourth resistor having a first end being connected to a first end of the second resistor;

a first transistor, a second end of the third resistor being connected to a base or gate of the first transistor; and

a second transistor, a second end of the fourth resistor being connected to a base or gate of the second transistor, wherein

a direct-current voltage is supplied to a connection point between the first resistor and the third resistor, a connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor, from a voltage supply point through a ground element, and

the differential signal processing circuit performs the predetermined differential signal processing using a bias current supplied from a second end of each of the first resistor and the second resistor.

15. The differential signal processing apparatus according to claim 14, wherein the differential signal processing circuit includes:

a third transistor, the second end of the first resistor being connected to a base or gate of the third transistor, an emitter or source of the third transistor being grounded at high frequencies; and

a fourth transistor, the second end of the second resistor being connected to a base or gate of the fourth transistor, an emitter or source of the fourth transistor being grounded at high frequencies, and

the third and fourth transistors amplify signals differentially inputted to the bases or gates thereof, and then output the amplified signals from collectors or drains thereof.

16. The differential signal processing apparatus according to claim 14, wherein the differential signal processing circuit includes:

a third transistor, the second end of the first resistor being connected to a base or gate of the third transistor, a collector or drain of the third transistor being connected to a predetermined potential; and

a fourth transistor, the second end of the second resistor being connected to a base or gate of the fourth transistor, a collector or drain of the fourth transistor being connected to a predetermined potential, and

the third and fourth transistors perform an impedance conversion on signals differentially inputted to the bases or gates thereof, and then output the signals from emitters or sources thereof.

17. The differential signal processing apparatus according to claim 14, wherein the differential signal processing circuit includes:

a third transistor, the second end of the first resistor being connected to a base or gate of the third transistor; and

a fourth transistor, the second end of the second resistor being connected to a base or gate of the fourth transistor, an emitter or source of the fourth transistor being connected to an emitter or source of the third transistor, and

the third and fourth transistors allow a first signal to be inputted to the emitter or source thereof, allow second signals to be differentially inputted to the bases or gates thereof, mix the first and second signals, and then output the mixed signal from a collector or drain thereof.

18. The differential signal processing apparatus according to claim 17, wherein the differential signal processing circuit further includes:

a fifth transistor, the second end of the second resistor being connected to a base or gate of the fifth transistor; and

a sixth transistor, the second end of the first resistor being connected to a base or gate of the sixth transistor, an emitter or base of the sixth transistor being connected to an emitter or source of the fifth transistor, and

the fifth and sixth transistors allow the first signal to be inputted in reverse phase to the emitter or source thereof, allow the second signals to be differentially inputted to the bases or gates thereof, mix the first signal in reverse phase and the second signals, and then output the mixed signals from collectors or drains thereof.

19. The differential signal processing apparatus according to claim 14, wherein the differential signal processing circuit includes:

a third transistor, the second end of the first resistor being connected to a base or gate of the third transistor, an emitter or source of the third transistor being grounded at high frequencies;

a fourth transistor, the second end of the second resistor being connected to a base or gate of the fourth transistor, and an emitter or source of the fourth transistor being grounded at high frequencies;

a first capacitor connecting the base or gate of the third transistor to a collector or drain of the fourth transistor; and

a second capacitor connecting the base or gate of the fourth transistor to a collector or drain of the third transistor, and

the emitter or source of each of the third and fourth transistors is grounded at high frequencies, and the third and fourth transistors output oscillated differential signals from the collectors or drains thereof.

20. The differential signal processing apparatus according to claim 15, wherein the ground element includes:

a fifth resistor connecting the connection point between the first resistor and the third resistor and the collector or drain of the first transistor to the voltage supply point; and

a sixth resistor connecting the connection point between the second resistor and the fourth resistor and the collector or drain of the second transistor to the voltage supply point.

21. The differential signal processing apparatus according to claim 15, wherein the ground element includes:

a fifth resistor connecting the collector or drain of the first transistor to the voltage supply point;

a sixth resistor connecting the collector or drain of the second transistor to the voltage supply point;

a fifth transistor, a base or gate of the fifth transistor being connected to the collector or drain of the first transistor, and an emitter or source of the fifth transistor being connected to the connection point between the first resistor and the third resistor;

a sixth transistor, a base or gate of the sixth transistor being connected to the collector or drain of the second transistor, and an emitter or source of the sixth transistor being connected to the connection point between the second resistor and the fourth resistor;

a first capacitor connecting the collector or drain of the first transistor to an emitter or source of the first transistor; and

a second capacitor connecting the collector or drain of the second transistor to an emitter or source of the second transistor.

22. The differential signal processing apparatus according to claim 15, wherein the ground element includes:

a fifth resistor connecting the collector or drain of the first transistor and the collector or drain of the second transistor to the voltage supply point;

a fifth transistor, a base or gate of the fifth transistor being connected to the collector or drain of the first transistor, and an emitter or source of the fifth transistor being connected to the connection point between the first resistor and the third resistor; and

a sixth transistor, a base or gate of the sixth transistor being connected to the collector or drain of the second transistor, and an emitter or source of the sixth transistor being connected to the connection point between the second resistor and the fourth resistor.

23. The differential signal processing apparatus according to claim 15, wherein the first to fourth transistors are selected from the group consisting of an NPN bipolar transistor and an N-channel MOS field-effect transistor.

24. The differential signal processing apparatus according to claim 23, wherein the emitter or source of each of the first to fourth transistors is grounded.

25. The differential signal processing apparatus according to claim 23, wherein the emitter or source of each of the first to fourth transistors is grounded through a resistor.

26. The differential signal processing apparatus according to claim 23, wherein the emitter or source of each of the first to fourth transistors is grounded through an inductor.

27. The differential signal processing apparatus according to claim 15, wherein the first to fourth transistors are selected from the group consisting of a PNP bipolar transistor and a P-channel MOS field-effect transistor.

28. The differential signal processing apparatus according to claim 27, wherein the emitter or source of each of the first to fourth transistors is connected to the voltage supply point.

29. The differential signal processing apparatus according to claim 27, wherein the emitter or source of each of the first to fourth transistors is connected to the voltage supply point via a resistor.

30. The differential signal processing apparatus according to claim 27, wherein the emitter or source of each of the first to fourth transistors is connected to the voltage supply point via an inductor.

31. The differential signal processing apparatus according to claim 15, wherein a connection from the ground element to the voltage supply point or a ground point is established by a signal wire.

32. The differential signal processing apparatus according to claim 15, wherein the differential signal processing circuit further includes:

a fifth transistor, a predetermined potential being connected to a base or gate of the fifth transistor, the collector or drain of the third transistor being connected to an emitter or source of the fifth transistor; and

a sixth transistor, the predetermined potential being connected to a base or gate of the sixth transistor, the collector or drain of the fourth transistor being connected to an emitter or source of the sixth transistor, and

signals differentially inputted to the bases or gates of the third and fourth transistors, respectively, are amplified and outputted from collectors or drains of the fifth and sixth transistors.

33. The differential signal processing apparatus according to claim 32, wherein

the collector or drain of the fifth transistor is connected to the base or gate of the third transistor via a first feedback circuit, and

the collector or drain of the sixth transistor is connected to the base or gate of the fourth transistor via a second feedback circuit.

34. The differential signal processing apparatus according to claim 33, wherein the first and second feedback circuits each are a series circuit including resistors connected in series.

35. The differential signal processing apparatus according to claim 33, wherein the first and second feedback circuits each are a parallel circuit including a resistor and a capacitor connected in parallel.

36. A radio circuit apparatus comprising:

a duplexer allowing use of an antenna for both transmission and reception;

a first oscillator using a first differential signal processing apparatus comprising a low-noise differential bias circuit for generating a low-noise bias current; and

a differential signal processing circuit for performing predetermined differential signal processing wherein

the low-noise differential bias circuit includes;

a first resistor;

a second resistor;

a third resistor having a first end being connected to a first end of the first resistor;

a fourth resistor having a first end being connected to a first end of the second resistor;

a first transistor, a second end of the third resistor being connected to a base or gate of the first transistor; and

a second transistor, a second end of the fourth resistor being connected to a base or gate of the second transistor, wherein

a direct-current voltage is supplied to a connection point between the first resistor and the third resistor a connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor, from a voltage supply point through a ground element, and

the differential signal processing circuit performs the predetermined differential signal processing using a bias current supplied from a second end of each of the first resistor and the second resistor, and

wherein the differential signal processing circuit includes;

a third transistor, the second end of the first resistor being connected to a base or gate of the third transistor, an emitter or source of the third transistor being grounded at high frequencies;

a fourth transistor, the second end of the second resistor being connected to a base or gate of the fourth transistor, and an emitter or source of the fourth transistor being grounded at high frequencies;

a first capacitor connecting the base or gate of the third transistor to a collector or drain of the fourth transistor; and

a second capacitor connecting the base or gate of the fourth transistor to a collector or drain of the third transistor, and

the emitter or source of each of the third and fourth transistors is grounded at high frequencies, and the third and fourth transistors output oscillated differential signals from the collectors or drains thereof;

a first amplifier using a second differential signal processing apparatus of claim 15, the first amplifier amplifying a receive signal to be outputted from the duplexer;

a demodulator using a third differential signal processing apparatus comprising a low-noise differential bias circuit for generating a low-noise bias current; and

a differential signal processing circuit for performing predetermined differential signal processing, wherein

the low-noise differential bias circuit includes;

a first resistor;

a second resistor;

a third resistor having a first end being connected to a first end of the first resistor;

a fourth resistor having a first end being connected to a first end of the second resistor;

a first transistor, a second end of the third resistor being connected to a base or gate of the first transistor; and

a second transistor, a second end of the fourth resistor being connected to a base or gate of the second transistor, wherein

a direct-current voltage is supplied to a connection point between the first resistor and the third resistor, a connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor, from a voltage supply point through a ground element, and

the differential signal processing circuit performs the predetermined differential signal processing using a bias current supplied from a second end of each of the first resistor and the second resistor,

wherein the differential signal processing circuit includes;

a third transistor, the second end of the first resistor being connected to a base or gate of the third transistor; and

a fourth transistor, the second end of the second resistor being connected to a base or gate of the fourth transistor, an emitter or source of the fourth transistor being connected to an emitter or source of the third transistor, and

the third and fourth transistors allow a first signal to be inputted to the emitter or source thereof, allow second signals to be differentially inputted to the bases or gates thereof, mix the first and second signals, and then output the mixed signal from a collector or drain thereof, and

wherein the differential signal processing circuit further includes;

a fifth transistor, the second end of the second resistor being connected to a base or gate of the fifth transistor; and

a sixth transistor, the second end of the first resistor being connected to a base or gate of the sixth transistor, an emitter or base of the sixth transistor being connected to an emitter or source of the fifth transistor, and

the fifth and sixth transistors allow the first signal to be inputted in reverse phase to the emitter or source thereof, allow the second signals to be differentially inputted to the bases or gates thereof mix the first signal in reverse phase and the second signals, and then output the mixed signals from collectors or drains thereof, the demodulator demodulating the amplified receive signal using a signal generated in the first oscillator;

a second oscillator using the first differential signal processing apparatus;

a modulator using the third differential signal processing apparatus, the modulator modulating a transmit signal using a signal generated in the second oscillator; and

a second amplifier using the second differential signal processing apparatus, the second amplifier amplifying the transmit signal outputted from the modulator and then outputting the amplified transmit signal to the duplexer.

37. The radio circuit apparatus according to claim 36, further comprising a control circuit for controlling, when a signal is transmitted, the second amplifier, the second oscillator, and the modulator to increase a transmission power of the transmit signal, and also controlling the first amplifier, the first oscillator, and the demodulator to increase consumption currents of the first amplifier, the first oscillator, and the demodulator.

38. The radio circuit apparatus according to claim 36, further comprising a control circuit for controlling, when a signal is not transmitted, the second amplifier, the second oscillator, and the modulator to reduce a transmission power of a transmit signal, and also controlling the first amplifier, the first oscillator, and the demodulator to reduce consumption currents of the first amplifier, the first oscillator, and the demodulator.

39. The radio circuit apparatus according to claim 36, further comprising:

a coupler for extracting a part of the transmit signal outputted from the second amplifier;

a level detection circuit for detecting a power level of the extracted transmit signal; and

a control circuit for changing consumption currents of the first amplifier, the first oscillator, and the demodulator based on the detected power level, wherein

the control circuit controls the consumption currents of the first amplifier, the first oscillator, and the demodulator such that the consumption currents increase as the detected power level increases.

40. The radio circuit apparatus according to claim 36, further comprising:

a coupler for extracting a part of the transmit signal outputted from the second amplifier;

a level detection circuit for detecting a power level of the extracted transmit signal; and

a control circuit for changing consumption currents of the first amplifier, the first oscillator, and the demodulator based on the detected power level, wherein

the control circuit controls the consumption currents of the first amplifier, the first oscillator, and the demodulator such that the consumption currents decrease as the detected power level decreases.

41. The radio circuit apparatus according to claim 36, further comprising:

a level detection circuit for allowing the receive signal outputted from the first amplifier to be inputted thereto, and then detecting a power level of the receive signal; and

a control circuit for changing consumption currents of the first amplifier, the first oscillator, and the demodulator based on the detected power level, wherein

the control circuit controls the consumption currents of the first amplifier, the first oscillator, and the demodulator such that the consumption currents increase as the detected power level increases.

42. The radio circuit apparatus according to claim 36, further comprising:

a level detection circuit for allowing the receive signal outputted from the first amplifier to be inputted thereto, and then detecting a power level of the receive signal; and

a control circuit for changing consumption currents of the first amplifier, the first oscillator, and the demodulator based on the detected power level, wherein

the control circuit controls the consumption currents of the first amplifier, the first oscillator, and the demodulator such that the consumption currents decrease as the detected power level decreases.

43. The radio circuit apparatus according to claim 36, further comprising:

a level detection circuit for allowing the receive signal outputted from the first amplifier and the receive signal outputted from the demodulator to be inputted thereto, and then detecting and comparing power levels of the two receive signals; and

a control circuit for changing consumption currents of the first amplifier, the first oscillator, and the demodulator based on a power level difference obtained through the comparison of the two receive signals, wherein

the control circuit controls the consumption currents of the first amplifier, the first oscillator, and the demodulator such that the consumption currents increase as the power level difference increases.

44. The radio circuit apparatus according to claim 36, further comprising:

a level detection circuit for allowing the receive signal outputted from the first amplifier and the receive signal outputted from the demodulator to be inputted thereto, and then detecting and comparing power levels of the two receive signals; and

a control circuit for changing consumption currents of the first amplifier, the first oscillator, and the demodulator based on a power level difference obtained through the comparison of the two receive signals, wherein

the control circuit controls the consumption currents of the first amplifier, the first oscillator, and the demodulator such that the consumption currents decrease as the power level difference decreases.