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System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative COMMON BUS protocol

  • US 20050165995A1
  • Filed: 03/17/2005
  • Published: 07/28/2005
  • Est. Priority Date: 03/15/2001
  • Status: Active Grant
First Claim
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1. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;

  • the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;

    the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a write transaction to transfer one or more data from the external bus to a peripheral resource assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module, each spanning preferably a period of said master clock cycle;

    a) issuing on the common bus a wait-write-and-query command at the start of a new write transaction towards an addressed peripheral resource to have returned on the common bus a remote filling status stating the number of memory locations before the addressed peripheral resource become full; and

    looping the following steps until detecting the assertion of a terminating signal to end the write transaction;

    b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the external bus to the main module;

    c) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for asserting an handshake ready signal causing a datum be transferred from the external to the common bus, or assuming a null local filling status value as a condition for issuing a command to terminate the current write transaction;

    d) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for issuing to the addressed resource a write-and-query command to transfer a datum from the common bus to a peripheral resource coupled to the destination macro-cell and to have returned on the common bus the remote filling status of the addressed resource, or assuming a null local filling status value as a condition for issuing a wait-write-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status.

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