System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative COMMON BUS protocol
First Claim
1. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a write transaction to transfer one or more data from the external bus to a peripheral resource assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module, each spanning preferably a period of said master clock cycle;
a) issuing on the common bus a wait-write-and-query command at the start of a new write transaction towards an addressed peripheral resource to have returned on the common bus a remote filling status stating the number of memory locations before the addressed peripheral resource become full; and
looping the following steps until detecting the assertion of a terminating signal to end the write transaction;
b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the external bus to the main module;
c) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for asserting an handshake ready signal causing a datum be transferred from the external to the common bus, or assuming a null local filling status value as a condition for issuing a command to terminate the current write transaction;
d) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for issuing to the addressed resource a write-and-query command to transfer a datum from the common bus to a peripheral resource coupled to the destination macro-cell and to have returned on the common bus the remote filling status of the addressed resource, or assuming a null local filling status value as a condition for issuing a wait-write-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status.
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Abstract
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.
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Citations
15 Claims
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1. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a write transaction to transfer one or more data from the external bus to a peripheral resource assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module, each spanning preferably a period of said master clock cycle;
a) issuing on the common bus a wait-write-and-query command at the start of a new write transaction towards an addressed peripheral resource to have returned on the common bus a remote filling status stating the number of memory locations before the addressed peripheral resource become full; and
looping the following steps until detecting the assertion of a terminating signal to end the write transaction;
b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the external bus to the main module;
c) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for asserting an handshake ready signal causing a datum be transferred from the external to the common bus, or assuming a null local filling status value as a condition for issuing a command to terminate the current write transaction;
d) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for issuing to the addressed resource a write-and-query command to transfer a datum from the common bus to a peripheral resource coupled to the destination macro-cell and to have returned on the common bus the remote filling status of the addressed resource, or assuming a null local filling status value as a condition for issuing a wait-write-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
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2. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface, through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a read transaction to transfer one or more data from a prefetchable peripheral resource to the external bus, being the prefetchable resources assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module each spanning preferably a period of said master clock cycle;
a) issuing on the common bus a wait-read-and-query command at the start of a new read transaction towards an addressed peripheral resource to have returned on the common bus a remote filling status stating the number of memory locations before the addressed peripheral resource become empty; and
looping the following steps until detecting the assertion of a terminating signal to terminate the read transaction;
b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the main module to the external bus;
c) checking if said local filling status is greater than zero;
checking if a further filling status stating the number of memory locations before a centralized memory FIFO inside the main module become full to write or empty to read is lower than a precautionary filling-up threshold;
taking both the checked conditions true as a criterion for issuing to the addressed peripheral resource coupled to the data originating macro-cell a read-and-query command to have returned on the common bus a single datum coupled to the remote filling status of the addressed peripheral resource, being the returned datum transferred directly to the centralized memory FIFO;
whether the criterion is not true issuing a wait-read-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status;
d) checking if at least a valid datum to be read is present inside said centralized memory FIFO and if that is true, asserting an handshake ready signal for transferring the datum to be read from said centralized memory FIFO to the external bus;
e) checking if said local filling status and the reading filling status of the centralized memory FIFO are both null and, if that is true, asserting a signal to terminate the current read transaction;
f) checking if said terminating signal is asserted and, if that is true, issuing a command for clearing out the centralized memory FIFO content at the end of the current read transaction, in such that an empty centralized buffer is assigned at a successive peripheral requester. - View Dependent Claims (4, 5, 6, 15)
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface, through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
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3. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface, through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a read transaction to transfer one or more data from a prefetchable peripheral resource to the external bus, being the prefetchable resources assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module each spanning preferably a period of said master clock cycle;
a) issuing on the common bus a read-and-query command at the start of a new read transaction towards an addressed peripheral resource to have returned on the common bus either a datum coupled with a remote filling status stating the number of memory locations before the addressed peripheral resource become empty, or the only filling status null; and
looping the following steps until detecting the assertion of a terminating signal to terminate the read transaction;
b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the main module to the external bus, by means of an arithmetic which bound each new calculated value of the local filling status to be greater or equal to zero;
c) checking if a further filling status stating the number of memory locations before a centralized memory FIFO inside the main module become full to write or empty to read is lower than a precautionary filling-up threshold, taking the true logic condition as a criterion for issuing to the addressed peripheral resource coupled to the data originating macro-cell a read-and-query command to have returned on the common bus either a datum coupled with a remote filling status stating the number of memory locations before the addressed peripheral resource become empty, or a remote filling status null, being the returned datum transferred to the centralized memory FIFO;
whether the criterion is not true issuing a wait-read-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status;
d) checking if at least a valid datum to be read is present inside said centralized memory FIFO and if that is true, asserting an handshake ready signal for transferring the datum to be read from said centralized memory FIFO to the external bus;
e) checking if said local filling status and the reading filling status of the centralized memory FIFO are both null and, if that is true, asserting a signal to terminate the current read transaction;
f) checking if said terminating signal is asserted and, if that is true, issuing a command for clearing out the centralized memory FIFO content at the end of the current read transaction, in such that an empty centralized buffer is assigned at a successive peripheral requester.
- the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface, through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;
Specification