System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative COMMON BUS protocol

• US 20050165995A1
• Filed: 03/17/2005
• Published: 07/28/2005
• Est. Priority Date: 03/15/2001
• Status: Active Grant

• Current Assignee: Italtel SPA (Italtel Group SPA)
• Original Assignee: Italtel SPA (Italtel Group SPA)
• Inventors: Gemelli, Riccardo, Blasio, Giuseppe De, Pavesi, Marco
• Granted Patent: US 7,130,942 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Claims

1. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;

the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;

the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a write transaction to transfer one or more data from the external bus to a peripheral resource assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module, each spanning preferably a period of said master clock cycle;

a) issuing on the common bus a wait-write-and-query command at the start of a new write transaction towards an addressed peripheral resource to have returned on the common bus a remote filling status stating the number of memory locations before the addressed peripheral resource become full; and

looping the following steps until detecting the assertion of a terminating signal to end the write transaction;

b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the external bus to the main module;

c) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for asserting an handshake ready signal causing a datum be transferred from the external to the common bus, or assuming a null local filling status value as a condition for issuing a command to terminate the current write transaction;

d) checking whether said local filling status is greater than zero and either assuming a positive value as a condition for issuing to the addressed resource a write-and-query command to transfer a datum from the common bus to a peripheral resource coupled to the destination macro-cell and to have returned on the common bus the remote filling status of the addressed resource, or assuming a null local filling status value as a condition for issuing a wait-write-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status.

7. An interface protocol in accordance with claim from 1, wherein said remote filling status is saturated at an integer greater than or preferably equal to the maximum round-trip delay of a transaction through the common bus expressed in number of master clock cycles.

8. An interface protocol in accordance with claim 1, wherein if a peripheral monitoring code corresponding to one out of many possible correlated replies that a selected peripheral resource returns to the main module is indicating a peripheral resource of not prefetchable type, like a FIFO, and the calculated local filling status of the addressed peripheral resource is null, then a wait cycle opportunely long is introduced to allow in the meanwhile a possible increasing of residual room in the peripheral resource for transfer some other data in the current transaction, by effect of the activity of the connected macro-cell.

9. An interface protocol in accordance with claim 8, wherein when a selected resource is not prefetchable a step is executed for calculating a delta filling status corresponding to a detected positive variation into said returned remote filling status incurred between two consecutive steps;

the delta filling status being added up to the previously defined local filling status.

10. An interface protocol in accordance with claim 1, wherein the protocol includes:

a step indefinitely iterated for monitoring handshake signals and commands on the external bus and generating in correspondence a set of converted signals recognizable by the main module of the interface, and

a step indefinitely iterated for converting into correspondent signals recognizable by an external protocol agent acting on the external bus an interface handshake signal and relevant protocol signals originated from the main module during said handshake steps for signaling that the main module is ready to transfer a datum or that a current transaction is terminated locally the interface.

11. An interface bus protocol in accordance with claim 10, wherein the protocol includes an indefinitely iterated general synchronization step in which:

incoming address, the set of converted signals recognizable by the main module, the remote filling status, the filling status of the centralized buffer, other relevant signals events and states inside the interface and at the boundaries directly detectable on the main module and on its incoming and outgoing common bus, are acquired and opportunely combined to match multiple logic conditions for issuing the right protocol commands and the relevant internal control signals relevant for executing said concurrent protocol steps for calculating delta and local filling status, executing read/write transactions towards the peripheral resources prefetchable and not prefetchable and handshaking them towards the external bus, and clear the centralized buffer.

12. An interface bus protocol in accordance with claim 1, wherein the protocol further includes the following steps:

an internal arbitration step among transaction requests issued from transaction requesters embedded into the macro-cells and connected to peripheral resources of the interface that forward the requests to a centralized internal arbiter for executing a weighted Round Robin arbitration algorithm which selects, one transaction request at a time;

as soon as one transaction request is selected a centralized request signal is asserted to enforce the main module to compete before an external arbiter for the master-ship of the external bus;

an indefinite number of wait steps for monitoring on the external bus the arrival of handshake signals indicating the main module either master of the external bus or the master-ship assigned to an external bus protocol agent and the main module slave consequently.

13. An interface bus protocol in accordance with claim 1, wherein the protocol further includes the following concurrent steps:

as soon as a grant signal indicating the main module master of the external bus is detected, the grant signal is prolonged to the peripheral resource, either prefetchable or not, associated to the selected transaction request;

at the only assertion of the grant signal a grant command is activated to start a grant cycle spanning few master clock cycles to retrieve useful DMA parameters from the respective transaction requester located into the user macro-cell associated to the granted peripheral resource;

as the DMA parameters are retrieved they are forwarded to the main module crossing the centralized buffer and stored into as many DMA registers, queued to the DMA parameters a read-and-query command is looped for filling up the centralized buffer;

being the main module master of the external bus and the centralized buffer full, the read transaction prosecutes and each looped read-and-query command while transfers to the external bus one datum extracted from the centralized buffer concurrently reads a datum from the granted peripheral resource and pushes it into the centralized buffer.

14. An interface bus protocol in accordance with claim 1, wherein the protocol further includes the following concurrent steps:

as soon as one transaction request is selected from the internal arbiter an internal grant signal is simultaneously asserted and assigned to the peripheral resource whose transaction request has been selected by the granting algorithm;

at the only assertion of the grant signal a grant command is activated to start a grant cycle spanning few master clock cycles to retrieve useful DMA parameters from the respective transaction requester located into the user macro-cell associated to the granted peripheral resource;

as the DMA parameters are retrieved they are forwarded to the main module crossing the centralized buffer and stored into as many DMA registers, queued to the DMA parameters a read-and-query command is looped for filling up the centralized buffer;

as soon as a grant signal is detected indicating the main module master of the external bus and being the centralized buffer full, the read transaction prosecutes and each looped read-and-query command while transfers to the external bus one datum extracted from the centralized buffer, concurrently reads a datum from the granted peripheral resource and pushes it into the centralized buffer;

as soon as a grant signal is detected indicating an external bus protocol agent master of the external bus and being the centralized buffer full, the main module answer by asserting a RETRAY signal on the external bus to declare its temporary impossibility to accept transactions and iterating the RETRAY signal until a favorable grant is detected.

2. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;

the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface, through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;

the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a read transaction to transfer one or more data from a prefetchable peripheral resource to the external bus, being the prefetchable resources assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module each spanning preferably a period of said master clock cycle;

a) issuing on the common bus a wait-read-and-query command at the start of a new read transaction towards an addressed peripheral resource to have returned on the common bus a remote filling status stating the number of memory locations before the addressed peripheral resource become empty; and

looping the following steps until detecting the assertion of a terminating signal to terminate the read transaction;

b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the main module to the external bus;

c) checking if said local filling status is greater than zero;

checking if a further filling status stating the number of memory locations before a centralized memory FIFO inside the main module become full to write or empty to read is lower than a precautionary filling-up threshold;

taking both the checked conditions true as a criterion for issuing to the addressed peripheral resource coupled to the data originating macro-cell a read-and-query command to have returned on the common bus a single datum coupled to the remote filling status of the addressed peripheral resource, being the returned datum transferred directly to the centralized memory FIFO;

whether the criterion is not true issuing a wait-read-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status;

d) checking if at least a valid datum to be read is present inside said centralized memory FIFO and if that is true, asserting an handshake ready signal for transferring the datum to be read from said centralized memory FIFO to the external bus;

e) checking if said local filling status and the reading filling status of the centralized memory FIFO are both null and, if that is true, asserting a signal to terminate the current read transaction;

f) checking if said terminating signal is asserted and, if that is true, issuing a command for clearing out the centralized memory FIFO content at the end of the current read transaction, in such that an empty centralized buffer is assigned at a successive peripheral requester.

4. An interface protocol in accordance with claim 2, wherein inside the reading loop:

a suitable residual read burst length counting is provided to further support read data burst transactions originated from a not prefetchable peripheral resource of FIFO type receiving data from a FIFO embedded into a macro-cell, the reading burst having a known length;

another concurrent step is provided in which the criterion stated at step c) is put in logical AND with a further condition stating that residual read burst length is greater than zero, being the new logical AND true as a global condition for issuing the read-and-query command;

the residual read burst length counting being unitary decremented for each new datum has been read.

5. An interface protocol in accordance with claim 2, wherein suitable flushing commands are provided to further support read data burst transactions originated from a traditional FIFO embedded into a macro-cell upstream a modified FIFO peripheral resource coupled to a logic which prevents data read in advance from the modified FIFO be overwritten until the reception of said flushing commands, and inside the reading loop:

an additional concurrent step similar to the step c) is provided and the new step differing from step c) mainly because said criterion is put in logical AND with a further condition stating that a prefixed number of data words have been definitely transferred to the external bus, being the true value of the new logical AND a global condition for issuing instead of the read-and-query command a flush command accompanied with an indication of said definitely transferred data words, the flush command flushing out from the modified FIFO the indicated number of data words and causes a repositioning of the modified FIFO'"'"'s internal pointers so that the unflushed words are considered unread;

step f) further includes a clear-and-flush command accompanied with a value stating the residual number of data definitely transferred to the external bus since the last issued flush command, the clear-and-flush command flushing out from the modified FIFO a number of data words equal to said residual number and causes a repositioning of the modified FIFO'"'"'s internal pointers so that the unflushed words are considered unread.

6. An interface protocol in accordance with claim 4, wherein the assertion of terminate signal at the step e) is delayed to concede time at the peripheral FIFO for receiving some other data from the macro-cell.

15. An interface bus protocol in accordance with claim 5, wherein the protocol further includes the following concurrent steps:

as soon as one transaction request is selected from the internal arbiter an internal grant signal is simultaneously asserted and assigned to the modified FIFO whose transaction request has been selected by the granting algorithm;

at the only assertion of the grant signal a grant command is activated to start a grant cycle spanning few master clock cycles to retrieve useful DMA parameters from the respective transaction requester located into the user macro-cell associated to the granted modified FIFO;

as the DMA parameters are retrieved they are forwarded to the main module crossing the centralized buffer and stored into as many DMA registers;

queued to the DMA parameters a read-and-query command is looped for filling up the centralized buffer;

as soon as a grant signal is detected indicating the main module master of the external bus and being the centralized buffer full, the read transaction prosecutes and each looped read-and-query command while transfers to the external bus one datum extracted from the centralized buffer, concurrently reads a datum from the granted modified FIFO and pushes it into the centralized buffer;

as soon as a grant signal is detected indicating an external bus protocol agent master of the external bus and being the centralized buffer full, the main module issues a clear-and-flush command accompanied with a parameter-flag and with a null value of words transferred on the external bus, to cause a repositioning of the modified FIFO'"'"'s internal pointers so that the data words transferred to the centralized buffer are considered unread and the DMA parameters are stored into the respective registers.

3. An interface protocol to manage two-way transactions between a microprocessor bus, or a local bus, and user macro-cells via an interposed interface;

the protocol including a plurality of concurrent steps synchronized at the master clock cycle of the interface for carrying out read/write transactions to transfer data between the two sides of the interface, through a main module of the interface connected both to an external bus coinciding with the microprocessor bus, or being the local bus, and an internal bus of the interface, named hereinafter common bus, further connected with prefetchable and not prefetchable peripheral resources constituting the remaining part of the interface coupled to the macro-cells;

the main module having indifferently the mastership of the external bus, or being slave, in both cases issuing protocol commands on the common bus and receiving back correlated replies, further exchanging arbitrate signals with an external arbiter and handshake signals with an external bus protocol agent, wherein a read transaction to transfer one or more data from a prefetchable peripheral resource to the external bus, being the prefetchable resources assigned to a subset of homogeneous resources belonging to one out of a plurality of standardizable peripheral modules clustered on the common bus, includes at least the following concurrent steps charged to the main module each spanning preferably a period of said master clock cycle;

a) issuing on the common bus a read-and-query command at the start of a new read transaction towards an addressed peripheral resource to have returned on the common bus either a datum coupled with a remote filling status stating the number of memory locations before the addressed peripheral resource become empty, or the only filling status null; and

looping the following steps until detecting the assertion of a terminating signal to terminate the read transaction;

b) calculating locally to the main module a local filling status by subtracting a unitary value to said returned remote filling status in case a datum has been transferred in the current step from the main module to the external bus, by means of an arithmetic which bound each new calculated value of the local filling status to be greater or equal to zero;

c) checking if a further filling status stating the number of memory locations before a centralized memory FIFO inside the main module become full to write or empty to read is lower than a precautionary filling-up threshold, taking the true logic condition as a criterion for issuing to the addressed peripheral resource coupled to the data originating macro-cell a read-and-query command to have returned on the common bus either a datum coupled with a remote filling status stating the number of memory locations before the addressed peripheral resource become empty, or a remote filling status null, being the returned datum transferred to the centralized memory FIFO;

whether the criterion is not true issuing a wait-read-and-query command for inserting a wait cycle on the common bus and have returned the remote filling status;

d) checking if at least a valid datum to be read is present inside said centralized memory FIFO and if that is true, asserting an handshake ready signal for transferring the datum to be read from said centralized memory FIFO to the external bus;

e) checking if said local filling status and the reading filling status of the centralized memory FIFO are both null and, if that is true, asserting a signal to terminate the current read transaction;

f) checking if said terminating signal is asserted and, if that is true, issuing a command for clearing out the centralized memory FIFO content at the end of the current read transaction, in such that an empty centralized buffer is assigned at a successive peripheral requester.