Integrated circuit random access memory capable of automatic internal refresh of memory array
First Claim
1. A random access memory integrated circuit responsive to an externally supplied clock input, the random access memory integrated circuit comprising:
- a dynamic memory array configured in one or more banks, wherein the dynamic memory array requires periodic refreshing to maintain data; and
one or more refresh control circuits generating refresh requests inside the random access memory integrated circuit, the dynamic memory array configured to receive read and write access requests, wherein the read or write access requests have priority over pending refresh requests, wherein one pending refresh request to one of the banks is retired on any clock cycle not requiring an access of that bank, the refresh completing in the clock cycle, the read access requests initiating an access to the dynamic memory array without first determining whether data is available from outside the dynamic memory array, thereby avoiding a delay associated with such determination.
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Accused Products
Abstract
A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.
72 Citations
20 Claims
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1. A random access memory integrated circuit responsive to an externally supplied clock input, the random access memory integrated circuit comprising:
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a dynamic memory array configured in one or more banks, wherein the dynamic memory array requires periodic refreshing to maintain data; and
one or more refresh control circuits generating refresh requests inside the random access memory integrated circuit, the dynamic memory array configured to receive read and write access requests, wherein the read or write access requests have priority over pending refresh requests, wherein one pending refresh request to one of the banks is retired on any clock cycle not requiring an access of that bank, the refresh completing in the clock cycle, the read access requests initiating an access to the dynamic memory array without first determining whether data is available from outside the dynamic memory array, thereby avoiding a delay associated with such determination. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification