Configurable width buffered module having switch elements

• US 20050166026A1
• Filed: 07/13/2004
• Published: 07/28/2005
• Est. Priority Date: 01/05/2000
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Tsern, Ely, Perego, Richard, Ware, Fred
• Granted Patent: US 7,404,032 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H05K 1/181 associated with surface mounted components

Abstract

A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one switch element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A switch element is positioned on or off a memory module and includes two transistors in embodiments of the invention. One or more switch elements are coupled to one or more channels to allow for upgrades of memory modules in a memory system. An asymmetrical switch topology allows for increasing the number of memory modules to more than two memory modules without adding switch elements serially on each channel. Switch elements allow for increasing the number of ranks of memory modules in a system, while also achieving many of the benefits associated with point-to-point topology.

Claims

1. A memory subsystem, comprising:

a first memory module including,

a first integrated circuit having memory including a first storage cell and a second storage cell,

a first buffer device coupled to the first integrated circuit;

a second memory module including,

a second integrated circuit having memory including a third storage cell and a fourth storage cell,

a second buffer device coupled to the second integrated circuit;

an interconnect including a first signal line and a second signal line; and

a first switch element coupling the second signal line to the first memory module, wherein the memory subsystem is operable in a first mode of operation and a second mode of operation, wherein;

during the first mode of operation, the first storage cell is accessible from the first signal line through the first buffer device and the second storage cell is accessible from the second signal line through the first switch element and the first buffer device, and

during the second mode of operation, the first storage cell is accessible from the first signal line through the first buffer device and the third storage cell is accessible from the second signal line through the first switch element and the second buffer device.

2. The memory subsystem of claim 1, wherein:

during the second mode of operation, at a second time, the second storage cell is accessible from the first signal line through the first buffer device and the third storage cell is accessible from the second signal line through the switch element and the second buffer device.

3. The memory subsystem of claim 1, further comprising:

a second switch element coupled to the first signal line and the first memory module.

4. The memory subsystem of claim 1, wherein the first switch element includes a first and second transistor.

5. The memory subsystem of claim 4, wherein the first transistor is an NMOS transistor and the second transistor includes a PMOS transistor.

6. The memory subsystem of claim 5, wherein the NMOS transistor has a gate and the PMOS transistor has a gate coupled to the NMOS gate.

7. A memory subsystem, comprising:

a first memory module including,

a first integrated circuit having memory including a first storage cell,

a second integrated circuit having memory including a second storage cell,

a first buffer device coupled to the first and second integrated circuits;

a second memory module including,

a third integrated circuit having memory including a third storage cell,

a fourth integrated circuit having memory including a fourth storage cell,

a second buffer device coupled to the third and fourth integrated circuits;

an interconnect including a first signal line and a second signal line; and

a first switch element coupling the second signal line to the first memory module, wherein the memory subsystem is operable in a first mode of operation and a second mode of operation, wherein;

during the first mode of operation, the first storage cell is accessible from the first signal line through the first buffer device and the second storage cell is accessible from the second signal line through the first switch element and the first buffer device, and

during the second mode of operation, the first storage cell is accessible from the first signal line through the first buffer device and the third storage cell is accessible from the second signal line through the first switch element and the second buffer device.

8. The memory subsystem of claim 7, wherein:

during the second mode of operation, at a second time the second storage cell is accessible from the first signal line through the first buffer and the fourth storage cell is accessible from the second signal line through the first switch element and the second buffer device.

9. The memory subsystem of claim 7, further comprising:

a second switch element coupled to the first signal line and the first memory module.

10. The memory subsystem of claim 7, wherein the first switch element includes a first and second transistor.

11. The memory subsystem of claim 10, wherein the first transistor is an NMOS transistor and the second transistor includes a PMOS transistor.

12. The memory subsystem of claim 11, wherein the NMOS transistor has a gate and the PMOS transistor has a gate coupled to the NMOS gate.

13. A memory subsystem, comprising:

a first memory module including,

a first integrated circuit having memory including a first, second and third storage cell,

a first buffer device coupled to the first integrated circuit;

a second memory module including,

a second integrated circuit having memory including a fourth storage cell,

a second buffer device coupled to the second integrated circuit;

an interconnect including a first signal line and a second signal line; and

a first switch element coupling the second signal line to the first memory module and the second memory module, wherein the memory subsystem is operable in a first mode of operation and a second mode of operation, wherein;

during the first mode of operation at a first time, the first storage cell is accessible from the first signal line through the first buffer device and the second storage cell is accessible from the second signal line through the first switch element and the first buffer device, and

during the second mode of operation at a second time, the third storage cell is accessible from the first signal line through the first buffer device and the fourth storage cell is accessible from the second signal line through the first switch element and the second buffer device.

14. The memory subsystem of claim 13, further comprising:

a second switch element coupled to the first signal line and the first memory module.

15. The memory subsystem of claim 13, wherein the first switch element includes a first and second transistor.

16. The memory subsystem of claim 15, wherein the first transistor is an NMOS transistor and the second transistor includes a PMOS transistor.

17. The memory subsystem of claim 16, wherein the NMOS transistor has a gate and the PMOS transistor has a gate coupled to the NMOS gate.

18. A memory subsystem, comprising:

a first memory module including,

a first integrated circuit having memory including a first and a third storage cell,

a second integrated circuit having memory including a second storage cell,

a first buffer device coupled to the first and second integrated circuits;

a second memory module including,

a third integrated circuit having memory including a fourth storage cell,

a second buffer device coupled to the third integrated circuit;

an interconnect including a first signal line and a second signal line; and

a first switch element coupling the second signal line to the first memory module, wherein the memory subsystem is operable in a first mode of operation and a second mode of operation, wherein;

during the first mode of operation at a first time, the first storage cell is accessible from the first signal line through the first buffer device and the second storage cell is accessible from the second signal line through the first switch element and the first buffer device, and

during the second mode of operation at a second time, the third storage cell is accessible from the first signal line through the first buffer device and the fourth storage cell is accessible from the second signal line through the first switch element and the second buffer device.

19. The memory subsystem of claim 18, further comprising:

a second switch element coupled to the first signal line and the first memory module.

20. The memory subsystem of claim 19, wherein the first switch element includes a first and second transistor.

21. The memory subsystem of claim 20, wherein the first transistor is an NMOS transistor and the second transistor includes a PMOS transistor.

22. The memory subsystem of claim 21, wherein the NMOS transistor has a gate and the PMOS transistor has a gate coupled to the NMOS gate.

23. A system, comprising:

a channel including a first signal line and a second signal line;

a memory module, coupled to the channel, having a buffer device and an integrated circuit including memory having a storage cell;

a switch element, coupled to the channel, to couple the first signal line to the second signal line in response to a select signal; and

,

a master, coupled to the first channel, to transfer data on the first channel.

24. The system of claim 23, wherein the controller generates the select signal.

25. The system of claim 23, wherein the switch element includes a first transistor and a second transistor.

26. A system, comprising:

a controller coupled to a first, second, third and fourth channel;

a first and second switch element coupled to the first channel;

a third and fourth switch element coupled to the second channel;

a fifth and sixth switch element coupled to the third channel;

a seventh and eighth switch element coupled to the fourth channel;

a ninth switch element coupled to the first switch element;

a tenth switch element coupled to the third switch element;

an eleventh switch element coupled to the fifth switch element;

a twelfth switch element coupled to the seventh switch element;

a first memory module coupled to the second, fourth, sixth and eighth switch elements;

a second memory module coupled to the second, fourth, sixth and eighth switch elements;

a third memory module coupled to the ninth, tenth, eleventh and twelfth switch elements; and

a fourth memory module coupled to the ninth, tenth, eleventh and twelfth switch elements.

27. An apparatus, comprising:

a first memory module;

a second memory module; and

means for switching information between the first and second memory modules in response to a select signal.