High-performance hybrid processor with configurable execution units

• US 20050166038A1
• Filed: 04/10/2002
• Published: 07/28/2005
• Est. Priority Date: 04/10/2002
• Status: Active Grant

• Current Assignee: Tensilica Incorporated
• Original Assignee: Tensilica Incorporated
• Inventors: Rowen, Christopher, Wang, Albert, Rosenthal, Bernard
• Granted Patent: US 7,200,735 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.

Claims

1. A hybrid processor design comprising:

a non-configurable base processor design with base processor instructions suitable for different applications, the non-configurable base processor design having;

a base resister file,

a base execution unit for executing base processor instructions, and

a first uni-directional datapath between the base register file and the base execution unit for providing base processor instruction operand data; and

a configurable logic design capable of implementing extended instructions that each perform a complex operation, the configurable logic design having;

an extended execution unit for execution extended instructions, and

a second uni-directional datapath between the base register file and the extended execution unit for providing extended instruction operand data.

2. The hybrid processor design of claim 1, in which a physical design of the base processor design uses one of custom logic and standard cell circuit design techniques, and the physical design of the configurable logic design uses another design technique that includes the usage of field programmable logic.

3. The hybrid processor design of claim 2, wherein the field programmable logic is implemented with RAM-based look-up tables.

4. The hybrid processor design of claim 2 wherein the physical design of the base processor design and the physical design of the configurable logic design are each implemented as a semiconductor device.

5. The hybrid processor design of claim 1, in which a physical design of the base processor design uses a custom logic circuit design technique, and the physical design of the configurable logic design uses another design technique that includes the usage of standard cell or gate-array logic circuits.

6. The hybrid processor design of claim 5 wherein the physical design of the base processor design and the physical design of the configurable logic design are each implemented as a semiconductor device.

7. The hybrid processor design of claim 1, wherein the base processor design has registers of 32 bits in width.

8. The hybrid processor design of claim 1, wherein the base processor design supports at least 16 general purpose registers and the base instruction format uses less than 32 bits.

9. The hybrid processor design of claim 1, wherein the extended execution unit of the configurable logic design has a pipeline depth of more than one cycle.

10. The hybrid processor design of claim 1, wherein at least one of the extended instructions operate on extended registers or extended register files in the configurable logic design.

11. The hybrid processor design of claim 1, wherein the configurable logic design further includes a third datapath having a width wider than registers of the base processor design for use by at least one of the extended instructions.

12. The hybrid processor design of claim 11, wherein the third datapath is used to compute the same operation in parallel on each of several operands within a data word.

13. The hybrid processor design of claim 11, wherein at least another one of the extended instructions use more than two source register specifiers.

14. The hybrid processor design of claim 1, wherein at least one of the extended instructions use more than two source register specifiers.

15. The hybrid processor design of claim 1, wherein at least one of the extended instructions compute more than one result.

16. The hybrid processor design of claim 1, wherein the configurable logic design is pipelined with a same clock as the base processor design.

17. The hybrid processor design of claim 1, wherein the base processor design has access via load and store operations to non-processor logic implemented in the configurable logic design.

18. The hybrid processor design of claim 1, further including at least another non-configurable base processor design with instructions suitable for different applications and wherein the non-configurable base processor design and the another non-configurable base processor design share the configurable logic design, and wherein extended instructions of the non-configurable base processor design and the another non-configurable base processor design are implemented in the configurable logic design.

19. The hybrid processor design of claim 1, wherein the extended instructions have direct access to non-processor logic implemented in the configurable logic design to serve as source operands to instructions.

20. The hybrid processor design of claim 1, wherein results of extended instructions are directly available to non-processor logic implemented in the configurable logic design.

21. The hybrid processor design of claim 1, wherein some of the extended instructions are selected by a user configuring the configurable logic design by choosing from a menu of pre-defined optional instructions.

22. The hybrid processor design of claim 1, wherein some of the extended instructions are defined using an instruction description language.

23. The hybrid processor design of claim 1, wherein some of the extended instructions are defined by a software program analyzing an application written in a high level language.

24. The hybrid processor design of claim 1, wherein some of the extended instructions are obtained based upon profiling an application to determine performance-critical sections.

25. The hybrid processor design of claim 1 when pipeline interlocks or bypass within the base processor design are computed using instruction templates.

26. The hybrid processor design of claim 1, wherein the base processor design and the configurable logic design are implemented together on a single semiconductor substrate.

27. The hybrid processor design of claim 1, wherein the base processor design, the configurable logic design and other configurable or non-configurable logic functions or memories are implemented together on a single semiconductor substrate.

28. The hybrid processor design of claim 1, wherein the configurable logic design runs asynchronously to the base processor design, and certain signals going between the configurable logic design and the base processor design pass through at least one synchronizing circuit.

29. The hybrid processor design of claim 1 wherein the configurable logic design is reconfigurable.

30. The hybrid processor design of claim 1 wherein the configurable logic design further includes extended register files.

64. A hybrid processor design according to claim 1, wherein the base processor design includes a first plurality of pipe stages, and the configurable processor design includes a second plurality of pipe stages different than the base processor design.

65. A hybrid processor design according to claim 1, wherein the extended instructions include an instruction format number that defines the location and size of all register specifiers for the extended instructions.

66. A hybrid processor design according to claim 1, wherein the extended instructions include a pipeline set identifier that defines a first pipe stage in which a source operated is required and a second pipe stage in which a result is generated.

67. A hybrid processor design according to claim 1, wherein the first and second uni-directional datapaths provide operand data within one cycle of the base execution unit and extended instruction unit, respectively.

68. A hybrid processor design according to claim 1, wherein the base execution unit and extended execution unit operate at first and second clocks, respectively, that are kept in synchronization.

69. A hybrid processor design according to claim 68, wherein the first and second clocks have the same frequency.

70. A hybrid processor design according to claim 68, wherein the first clock is an integer multiple of the second clock.

31. A method of making a hybrid processor design comprising the steps of:

providing a non-configurable base processor design with base processor instructions suitable for different applications, including providing the non-configurable base processor design with;

a base register file,

a base execution unit for executing base processor instructions, and

a first uni-directional datapath between the bass register file and the base execution unit for providing base processor instruction operand data; and

determining a configurable logic design capable of implementing extended instructions that each perform a complex operation, thereby obtaining the hybrid processor design, including providing the configurable logic design with;

an extended execution unit for executing extended instructions, and

a second unidirectional datapath between the base register file and the extended execution unit for providing extended instruction operand data.

32. The method of claim 31, further including the steps of:

implementing the non-configurable base processor design using one of custom logic and standard cell circuit design techniques; and

implementing the configurable logic design using another design technique that includes the usage of field programmable logic.

33. The method of claim 32, wherein the step of implementing implements the field programmable logic with RAM-based look-up tables.

34. The method of claim 32 wherein the steps of implementing implement the base processor design and the configurable logic design as a semiconductor device.

35. The method of claim 31, further including the steps of:

implementing the base processor design using a custom logic circuit design technique; and

implementing the configurable logic design using another design technique that includes the usage of standard cell or gate-array logic circuits.

36. The method of claim 35 wherein the steps of implementing implement the base processor design and the configurable logic design as a semiconductor device.

37. The method of claim 31, wherein the step of determining the configurable logic design includes providing the extended execution unit with a pipeline depth of more than one cycle.

38. The method of claim 31, wherein the step of determining the configurable logic design includes providing at least one of the extended instructions that operate on extended registers or extended register files.

39. The method of claim 31, wherein the step of determining the configurable logic design includes providing third data path wider than registers of the base processor design for use by at least one of the extended instructions.

40. The method of claim 39, wherein the step of determining the configurable logic design includes providing at least another one of the extended instructions that use more than two source register specifiers.

41. The method of claim 31, wherein the step of determining the configurable logic design includes providing at least one of the extended instructions that use more than two source register specifiers.

42. The method of claim 31, wherein the step of determining the configurable logic design includes providing at least one of the extended instructions that compute more than one result.

43. The method of claim 31, wherein the step of determining the configurable logic design includes providing a pipeline within the configurable logic design that is clocked with a same clock as the base processor design.

44. The method of claim 31, wherein the step of providing the base processor design includes providing the base processor design with access via load and store operations to non-processor logic implemented in the configurable logic design.

45. The method of claim 31, further including the step of providing at least another non-configurable base processor design with instructions suitable for different applications and wherein the non-configurable base processor design and the another non-configurable base processor design share the configurable logic design, and wherein extended instructions of the non-configurable base processor design and the another non-configurable base processor design are implemented in the configurable logic design.

46. The method of claim 31, wherein the step of determining the configurable logic design includes providing extended instructions that have direct access to non-processor logic implemented in the configurable logic design to serve as source operands to instructions.

47. The method of claim 31, wherein the step of determining the configurable logic design includes providing results of extended instructions that are directly available to non-processor logic implemented in the configurable logic design.

48. The method of claim 31, wherein the step of determining the configurable logic design includes selecting some of the extended instructions by a user configuring the configurable logic design by choosing from a menu of pre-defined optional instructions.

49. The method of claim 31, wherein the step of determining the configurable logic design includes defining some of the extended instructions using an instruction description language.

50. The method of claim 31, wherein the step of determining the configurable logic design includes defining some of the extended instructions by a software program analyzing an application written in a high level language.

51. The method of claim 31, wherein the step of determining the configurable logic design includes obtaining some of the extended instructions based upon profiling an application to determine performance-critical sections.

52. The method of claim 31 wherein the step of providing the base processor design includes providing pipeline interlocks or bypass that are computed using instruction templates.

53. The method of claim 31 further including the step of implementing the base processor design and the configurable logic design together on a single semiconductor substrate.

54. The method of claim 31 further including the step of implementing the base processor design, the configurable logic design and other configurable or non-configurable logic functions or memories together on a single semiconductor substrate.

55. The method of claim 31 wherein the step of determining the configurable logic design includes providing that the configurable logic design run asynchronously to the base processor design, and further provides that certain signals going between the configurable logic design and the base processor design pass through at least one synchronizing circuit.

56. The method of claim 31 wherein the step of determining the configurable logic design includes providing that the configurable logic design is reconfigurable.

57. The method of claim 31 wherein the step of determining the configurable logic design includes providing extended register files.

58. A hybrid processor comprising:

a base processor for executing first instructions using first logic implemented in a first logic technology;

an extended execution unit for executing second instructions using second logic implemented in a second logic technology, the extended execution unit having a plurality of pipe stages; and

a hybrid bypass and interlock mechanism that coordinates behavior of the base processor and behavior of the extended execution unit so that instruction result data is passed correctly among the pipe stages of the extended execution unit and between the base processor and the extended execution unit.

59. A hybrid processor according to claim 58, wherein the second instructions each perform a complex operation.

60. A hybrid processor according to claim 59, wherein the complex operation comprises one of:

an instruction with processor memory as direct source or destination for operands;

an instruction with one or more stage registers or register files implemented in the second logic;

an instruction with a large number of register specifier fields;

an instruction with a basic format unlike a format of the base processor;

an instruction with latency greater than on processor clock cycle;

an instruction that operates on operands wider than a native width of the base processor; and

an instruction that combines more than one basic operand into a single source and/or result operand and performs operations on all basic operands in parallel.

61. A hybrid processor according to clam 58, wherein the hybrid bypass and interlock mechanism is adapted to stall the hybrid processor until awaited results are available to the first and second instructions.

62. A hybrid processor according to claim 61, wherein the hybrid bypass and interlock mechanism includes means for tracking source and destination registers for the first and second instructions at each pipeline stage of the base processor and the extended instruction unit.

63. A hybrid processor according to claim 61, wherein the hybrid bypass and interlock mechanism includes means for comparing, in a given pipe stage of the base processor and the extended instruction unit, a source register specifier required in that pipe stage against each destination register specifier intended for a register file corresponding to the source register specifier.