DSP bus monitoring apparatus and method

• US 20050166098A1
• Filed: 02/07/2005
• Published: 07/28/2005
• Est. Priority Date: 08/15/1997
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Henry A. Davis
• Inventors: Davis, Henry A.
• Granted Patent: US 7,272,678 B2
• Time in Patent Office: Days
• US Class Current: 714/45
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/364 tracing values on a bus

Abstract

A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store, in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Claims

1-10. -10. (canceled)

11. A method of monitoring the internal operation of a processor, said processor comprising a plurality of external interfaces and one or more internal buses, said internal buses not accessible from said interfaces, said method comprising:

providing a trigger condition input corresponding to an instruction of said processor;

providing a monitor input from at least one of said buses;

providing bus data from at least one of said buses;

generating a first trigger output when a trigger condition derived from said trigger condition input compares to a trigger event associated with said monitor input; and

generating a second trigger output to indicate a second trigger event has been observed.

12. The method of claim 11, wherein said trigger condition input corresponding to an instruction of said processor comprises an operational code (opcode).

13. The method of claim 12, wherein said opcode comprises an opcode present in a digital signal processor (DSP).

14. The method of claim 12, wherein said opcode comprises an opcode of a superscalar program.

15. The method of claim 12, wherein said opcode comprises an opcode of a branch or jump instruction.

16. The method of claim 12, further comprising providing a value on an address bus to one or more of said external interfaces.

17. The method of claim 11, wherein said trigger condition input corresponding to an instruction of said processor comprises one of a branch or jump instruction.

18. The method of claim 11, further comprising providing a value on an address bus to one or more of said external interfaces.

19. Apparatus adapted to monitor the internal operation of a processor, said processor comprising a plurality of external interfaces and one or more internal buses, said internal buses not accessible from said interfaces, said apparatus monitoring according to the method comprising:

providing a trigger condition input corresponding to an instruction of said processor;

providing a monitor input from at least one of said buses;

providing bus data from at least one of said buses;

generating a first trigger output when a trigger condition derived from said trigger condition input compares to a trigger event associated with said monitor input; and

generating a second trigger output to indicate a second trigger event has been observed.

20. Apparatus adapted to monitor the operation of a digital processor, said processor comprising at least one external interfaces and one or more internal buses, said internal buses not accessible from said at least one interface, said apparatus monitoring according to the method comprising:

detecting a trigger condition input corresponding to an operational code of said digital processor;

receiving a monitor input from at least one of said buses;

receiving bus data from at least one of said buses;

generating a first trigger output when a trigger condition derived from said trigger condition input compares to a trigger event associated with said monitor input; and

generating a second trigger output to indicate a second trigger event has been observed.