Generation of memory test patterns for DLL calibration

• US 20050166110A1
• Filed: 01/28/2004
• Published: 07/28/2005
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Greeff, Roy, Swanson, Travis
• Granted Patent: US 7,444,559 B2
• Time in Patent Office: Days
• US Class Current: 714/728
• CPC Class Codes: G01R 31/318328 for delay tests

Abstract

A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

Claims

1. A method of generating a signaling pattern for a bus having a plurality of bit lines, said method comprising:

for each selected bit line in said plurality of bit lines;

generating, using a first linear feedback shift register, a first plurality of signals to be sent over said selected bit line; and

further generating, using a second linear feedback shift register, a second plurality of signals to be sent over at least one bit line in said plurality of bit lines other than said selected bit line.

2. The method of claim 1, wherein said generating is performed simultaneously with said further generating.

3. The method of claim 1, wherein said first plurality of signals and said second plurality of signals are identical.

4. The method of claim 1, wherein the number of bit lines in said plurality of bit lines is 2^N, where N≧

1.

5. A method of signaling a bus having a plurality of bit lines, said method comprising:

transmitting a first plurality of signals on a selected one of said plurality of bit lines;

simultaneously transmitting a second plurality of signals on one or more of said plurality of bit lines other than said selected bit line; and

repeating said transmitting and simultaneously transmitting for each bit line in said plurality of bit lines.

6. The method of claim 5, wherein said first plurality of signals and said second plurality of signals are identical.

7. The method of claim 5, further comprising shifting said first plurality of signals by at least one bit from said second plurality of signals prior to said repeating.

8. A method of operating a memory connected to a bus, said method comprising:

transmitting a first plurality of signals on a selected one of a plurality of bit lines in said bus;

simultaneously transmitting a second plurality of signals on one or more of said plurality of bit lines other than said selected bit line; and

performing a data write/read operation at a data storage location in said memory using said bus while said signals in said transmitting and simultaneously transmitting are present on respective bit lines in said bus.

9. The method of claim 8, wherein said performing includes:

performing reading of data as part of said data write/read operation in conjunction with a strobe signal received from a delay locked loop.

10. The method of claim 9, further comprising:

configuring said delay locked loop to provide a delay to said strobe signal so as to enable latching of said data during reading thereof.

11. The method of claim 10, further comprising determining a duration of said delay based on accuracy of said data read during said data write/read operation.

12. The method of claim 11, further comprising repeating said transmitting, simultaneously transmitting, performing and determining for each bit line in said plurality of bit lines.

13. The method of 8, further comprising:

changing an operating condition of said memory, wherein said operating condition includes one or more of a supply voltage, a reference voltage, and temperature;

and

repeating said transmitting, simultaneously transmitting, and performing with said changed operating condition present.

14. A system comprising:

a memory chip;

a bus having a plurality of bit lines; and

a processor connected to said memory chip via said bus and in communication therewith through said bus, wherein said processor is configured to perform the following;

transmit a first plurality of data patterns on a selected one of said plurality of bit lines in said bus, and

transmit a second plurality of data patterns on one or more of said plurality of bit lines other than said selected bit line.

15. The system of claim 14, wherein said memory chip includes a plurality of memory cells to store data, and wherein said processor is configured to further perform a data write/read operation at one of said plurality of memory cells using said bus while said first and said second plurality of data patterns are present on respective bit lines in said bus.

16. The system of claim 15, wherein said processor includes a delay locked loop circuit configured to provide a delayed strobe signal during reading of data as part of said data write/read operation, and wherein said processor is configured to adjust a duration of delay for said delayed strobe signal based on accuracy of said data read during said data write/read operation.

17. The system of claim 14, wherein the number of bit lines in said plurality of bit lines is 2^N, where N≧

1.

18. The system of claim 14, wherein said processor is configured to transmit said first plurality of data patterns and said second plurality of data patterns simultaneously.

19. The system of claim 14, wherein said processor includes:

a first linear feedback shift register configured to generate said first plurality of data patterns; and

a second linear feedback shift register configured to generate said second plurality of data patterns.

20. The system of claim 14, wherein said processor further includes a decode circuit having a plurality of output lines, wherein each output line is configured to be connected to one of said plurality of bit lines so as to allow transmission of said first and said second plurality of bit patterns on respective bit lines.

21. The system of claim 14, wherein said processor is further configured to shift said first plurality of data patterns by at least one bit from said second plurality of data patterns.

22. The system of claim 14, wherein said processor is further configured to perform transmission of said first plurality of data patterns and said second plurality of data patterns for each bit line in said plurality of bit lines.

23. The system of claim 14, wherein said memory chip includes a plurality of memory cells to store data, and wherein said processor is configured to further perform a data write/read operation at one of said plurality of memory cells using said bus after each bit in said first and said second plurality of data patterns is transmitted on respective bit lines in said bus.