Imaging device having a pixel structure with high dynamic range read-out signal

• US 20050167602A1
• Filed: 01/06/2005
• Published: 08/04/2005
• Est. Priority Date: 02/09/1998
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: ON Semiconductor Image Sensor BVBA (Infineon Technologies AG)
• Inventors: Dierickx, Bart
• Granted Patent: US 8,063,963 B2
• Time in Patent Office: Days
• US Class Current: 250/370.10
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: H04N 25/571 involving a non-linear response
• CPC Class Codes: H04N 25/573 the logarithmic type
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A method obtains a read-out signal of a pixel having at least a photosensitive element with a charge storage node. The method includes the steps of acquiring charge carriers, converted from impinging radiation on the photosensitive element, on the charge storage node, applying during the integration period at least one reset pulse, resetting incompletely the charge carriers acquired at the moment of applying the reset pulse, to obtain at least one linear response region for the pixel, and driving the pixel in weak inversion after the last incomplete reset pulse of the integration period so as to obtain a logarithmic response part. A corresponding pixel is also described.

Claims

1. A method for obtaining a read-out signal of a pixel having at least a photosensitive element and a charge storage node, the method comprising the steps of while acquiring charge carriers on said charge storage node during an integration period, said charge carriers being converted from radiation impinging on the photosensitive element:

during a first time period of said integration period applying at least one reset pulse with a predetermined amplitude on said charge storage node, said pulse resetting incompletely the charge carriers acquired at the moment of applying said pulse; and

after each of at least one reset pulse further acquiring charge carriers on said charge storage node;

said method further comprising

driving said pixel in weak inversion during a second time period after the last incomplete reset pulse of said integration period;

further acquiring charge carriers on said charge storage node during said second time period.

2. The method according to claim 1, wherein a plurality of reset pulses is applied on the charge storage node during the first time period.

3. The method according to claim 2, wherein at least two of said plurality of reset pulses have different amplitudes.

4. The method according to claim 1, further comprising applying a reference signal on said charge storage node whereon said at least one reset pulse is superimposed.

5. The method according to claim 1, wherein said at least one reset pulse is delivered by a reset transistor, said reset transistor being in series with said photosensitive element.

6. The method according to claim 1, wherein the read-out signal is function of a combination of charges acquired prior and after application of said reset pulses.

7. The method according to claim 1, wherein said pixel is implemented in a MOS technology.

8. A pixel comprising:

a photosensitive element;

a charge storage node, for storing a signal from the photosensitive element at a moment in time; and

a reset terminal on a reset transistor, said reset terminal equipped for applying a pulsed reset signal to the reset transistor,

wherein said pixel further comprises driving means for driving the reset transistor in weak inversion.

9. A pixel according to claim 8, wherein said reset transistor is coupled in series with said photosensitive element.

10. A pixel according to claim 8, wherein said photosensitive element has an output node, said charge storage node being the output node of said photosensitive element.

11. A pixel according to claim 10, wherein said photosensitive element has a parasitic capacitor and wherein said charge storage node is the parasitic capacitor of the photosensitive element.

12. A pixel according to claim 8, wherein said pixel further comprises an amplifying element directly or indirectly connected to said charge storage node, the amplifying element amplifying or buffering the signal on said charge storage node for further signal processing.

13. A pixel according to claim 8, wherein said pixel is implemented in a MOS technology.