Memory cell with a vertical transistor and fabrication method thereof

• US 20050167721A1
• Filed: 05/14/2004
• Published: 08/04/2005
• Est. Priority Date: 01/30/2004
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Lin, Shian-Jyh, Hsu, Yu-Sheng
• Application Number:
  US10/845,909
• Publication Number:
  US 20050167721A1
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.

Claims

1. A memory cell with a vertical transistor, comprising:

a semiconductor silicon substrate comprising a deep trench, in which the deep trench comprises a first sidewall region and a second sidewall region;

a first insulating layer formed overlying the first sidewall region;

a second insulating layer formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer;

a gate electrode layer sandwiched between the first insulating layer and the second insulating layer; and

a buried strap out-diffusion region formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.

2. The memory cell with a vertical transistor as claimed in claim 1, wherein the second insulating layer contributes to a normal threshold voltage along the second sidewall region to turn on the vertical transistor, and the first insulating layer contributes to a higher threshold voltage along the first sidewall region without turning on the vertical transistor.

3. The memory cell with a vertical transistor as claimed in claim 1, further comprising a deep trench capacitor which comprises:

a first conductive layer filling the lower portion of the deep trench;

an ion-doped diffusion region formed in the substrate and surrounding the lower portion of the deep trench; and

a dielectric layer formed on the sidewall of the lower portion of the deep trench, and sandwiched between the first conductive layer and the ion doped diffusion region.

4. The memory cell with a vertical transistor as claimed in claim 3, further comprising:

a collar dielectric layer formed over the deep trench capacitor and overlying the first sidewall region and the second sidewall region of the deep trench;

a second conductive layer formed overlying the first conductive layer and surrounded by the collar dielectric layer, in which the top of the second conductive layer protrudes from the top of the collar dielectric layer;

a third conductive layer formed overlying the second conductive layer and the collar dielectric layer; and

a top insulating layer formed overlying the third conductive layer;

wherein, the first insulating layer is formed over the top insulating layer and overlying the first sidewall region of the deep trench;

wherein, the second insulating layer is formed over the top insulating layer and overlying the second sidewall region of the deep trench;

5. The memory cell with a vertical transistor as claimed in claim 4, wherein the collar dielectric layer is a silicon oxide layer.

6. The memory cell with a vertical transistor as claimed in claim 4, wherein the second conductive layer is an ion-doped polysilicon layer, and the third conductive layer is a polysilicon layer.

7. The memory cell with a vertical transistor as claimed in claim 4, wherein the top insulating layer is a silicon oxide layer.

8. The memory cell with a vertical transistor as claimed in claim 1, wherein the first insulating layer and the second insulating layer are silicon oxide layers.

9. The memory cell with a vertical transistor as claimed in claim 1, wherein the gate electrode layer is a polysilicon layer.

10. A fabrication method for a memory cell with a vertical transistor, comprising the steps of:

providing a semiconductor silicon substrate comprising a deep trench, in which the deep trench comprises a first sidewall region and a second sidewall region;

forming a first buried strap out-diffusion region and a second buried strap out-diffusion region in the substrate, in which the first buried strap out-diffusion region is adjacent to the first sidewall region of the deep trench, and the second buried strap out-diffusion region is adjacent to the second sidewall region of the deep trench;

forming a shielding layer to cover the second sidewall region of the deep trench;

using the shielding layer as a hard mask and performing an ion implantation process on the first sidewall region of the deep trench;

removing the shielding layer;

forming a first insulating layer on the first sidewall region of the deep trench, and forming a second insulating layer on the second sidewall region of the deep trench, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer; and

forming a gate electrode layer in the deep trench, in which the gate electrode layer is sandwiched between the first insulating layer and the second insulating layer;

wherein, the second buried strap out-diffusion region is located adjacent to the lower portion of the second insulating layer; and

wherein, the second insulating layer contributes to a normal threshold voltage along the second sidewall region for turning on the vertical transistor.

11. The fabrication method for a memory cell with a vertical transistor as claimed in claim 10, before the formation of the buried strap out-diffusion regions, further comprising the steps of:

forming a collar dielectric layer overlying the first sidewall region and the second sidewall region of the deep trench;

forming a second conductive layer in the deep trench and surrounded by the collar dielectric layer, in which the top of the second conductive layer protrudes from the top of the collar dielectric layer;

forming a third conductive layer overlying the second conductive layer and the collar dielectric layer; and

forming a top insulating layer overlying the third conductive layer;

wherein, the first buried strap out-diffusion region formed in the substrate adjacent to the first sidewall region of the deep trench is near the second conductive layer and the third conductive layer; and

wherein, the second buried strap out-diffusion region formed in the substrate adjacent to the second sidewall region of the deep trench is near the second conductive layer and the third conductive layer;

12. The fabrication method for a memory cell with a vertical transistor as claimed in claim 11, before the formation of the collar dielectric layer, further comprising the steps of:

forming an ion-doped diffusion region in the substrate and surrounding the lower portion of the deep trench;

forming a dielectric layer on the sidewall of the lower portion of the deep trench; and

forming a first conductive layer to fill the lower portion of the deep trench;

wherein, the ion-doped diffusion region surrounds the first conductive layer; and

wherein, the dielectric layer is sandwiched between the first conductive layer and the ion doped diffusion region.

13. The fabrication method for a memory cell with a vertical transistor as claimed in claim 10, wherein the shielding layer is a photoresist material which is hardened by an exposure process.

14. The fabrication method for a memory cell with a vertical transistor as claimed in claim 10, wherein the ion implantation uses fluorine as an ion source to perform tilt-angle implantation.

15. A memory cell with a vertical transistor, comprising:

a semiconductor silicon substrate comprising a deep trench, in which the deep trench comprises a first sidewall region and a second sidewall region;

a first collar dielectric layer formed overlying the first sidewall region;

a second collar dielectric layer formed overlying the second sidewall region;

a conductive layer formed in the deep trench and sandwiched by the first collar dielectric layer and the second collar dielectric layer, in which the conductive layer adjacent to the first sidewall region is partially covered by the first collar dielectric layer, and the conductive layer adjacent to the second sidewall region is fully covered by the second collar dielectric layer;

a top insulating layer formed overlying the conductive layer; and

a gate electrode layer sandwiched between the first insulating layer and the second insulating layer;

a buried strap out-diffusion region formed in the substrate adjacent to the first sidewall region, in which the buried strap out-diffusion region is located near the conductive layer;

a first insulating layer formed over the top insulating layer and overlying the first sidewall region of the deep trench;

a second insulating layer formed over the top insulating layer and overlying the second collar dielectric layer on the second sidewall region of the deep trench; and

a gate electrode layer formed in the deep trench and sandwiched by the first insulating layer and the second insulating layer.

16. The memory cell with a vertical transistor as claimed in claim 15, further comprising a deep trench capacitor which comprises:

a first polysilicon layer filling the lower portion of the deep trench;

an ion-doped diffusion region formed in the substrate and surrounding the lower portion of the deep trench; and

a dielectric layer formed on the sidewall of the lower portion of the deep trench, and sandwiched between the first polysilicon layer and the ion doped diffusion region.

17. The memory cell with a vertical transistor as claimed in claim 15, wherein each of the first collar dielectric layer and the second collar dielectric layer is a silicon oxide layer.

18. The memory cell with a vertical transistor as claimed in claim 15, wherein the conductive layer comprises:

a second polysilicon layer with ion dopants, in which the top of the second polysilicon layer protrudes from the top of the first collar dielectric layer, and the second polysilicon layer adjacent to the second sidewall region is fully covered by the second collar dielectric layer; and

a third polysilicon layer formed overlying the second polysilicon layer and covering the first collar dielectric layer.

19. The memory cell with a vertical transistor as claimed in claim 15, wherein the top insulating layer is a silicon oxide layer.

20. The memory cell with a vertical transistor as claimed in claim 15, wherein the first insulating layer and the second insulating layer is a silicon oxide layer.

21. The memory cell with a vertical transistor as claimed in claim 15, wherein the gate electrode layer is a polysilicon layer.

22. A fabrication method for a memory cell with a vertical transistor, comprising the steps of:

providing a semiconductor silicon substrate comprising a deep trench, in which the deep trench comprises a first sidewall region and a second sidewall region;

forming a first collar dielectric layer on the first sidewall region of the deep trench;

forming a second collar dielectric layer on the second sidewall region of the deep trench;

forming a first conductive layer in the deep trench, in which the first conductive layer is sandwiched by the first collar dielectric layer and the second dielectric layer;

forming a shielding layer to cover the second collar dielectric layer on the second sidewall region;

using the shielding layer as a hard mask and removing the first collar dielectric layer until the top of the first conductive layer protrudes from the top of the first collar dielectric layer;

removing the shielding layer;

forming a second conductive layer overlying the first conductive layer and the first collar dielectric layer, in which the second conductive layer adjacent to the second sidewall region is fully covered by the second collar dielectric layer;

forming a top insulating layer overlying the second conductive layer;

forming a buried strap out-diffusion region in the substrate adjacent to the first sidewall region of the deep trench, in which the buried strap out-diffusion region is located near the second conductive layer;

forming a first insulating layer overlying the first sidewall region of the deep trench;

forming a second insulating layer overlying the second collar dielectric layer on the second sidewall region; and

forming a gate electrode layer in the deep trench and sandwiched by the first insulating layer and the second insulating layer.

23. The fabrication method for a memory cell with a vertical transistor as claimed in claim 22, before the formation of the first collar dielectric layer and the second collar dielectric layer, further comprising the steps of:

forming an ion-doped diffusion region in the substrate and surrounding the lower portion of the deep trench;

forming a dielectric layer on the sidewall of the lower portion of the deep trench; and

forming a polysilicon layer to fill the lower portion of the deep trench;

wherein, the ion-doped diffusion region surrounds the first conductive layer; and

wherein, the dielectric layer is sandwiched between the polysilicon layer and the ion doped diffusion region.

24. The fabrication method for a memory cell with a vertical transistor as claimed in claim 22, wherein the shielding layer is a photoresist material which is hardened by an exposure process.

25. The fabrication method for a memory cell with a vertical transistor as claimed in claim 22, wherein the first collar dielectric layer and the second collar dielectric layer are silicon oxide layers.

26. The fabrication method for a memory cell with a vertical transistor as claimed in claim 22, wherein the first conductive layer is an ion-doped polysilicon layer, and the second conductive layer is a polysilicon layer.

27. The fabrication method for a memory cell with a vertical transistor as claimed in claim 22, wherein the top insulating layer is a silicon oxide layer.

28. The fabrication method for a memory cell with a vertical transistor as claimed in claim 22, wherein the first insulating layer and the second insulating layer are silicon oxide layers.