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Memory cell with a vertical transistor and fabrication method thereof

  • US 20050167721A1
  • Filed: 05/14/2004
  • Published: 08/04/2005
  • Est. Priority Date: 01/30/2004
  • Status: Abandoned Application
First Claim
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1. A memory cell with a vertical transistor, comprising:

  • a semiconductor silicon substrate comprising a deep trench, in which the deep trench comprises a first sidewall region and a second sidewall region;

    a first insulating layer formed overlying the first sidewall region;

    a second insulating layer formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer;

    a gate electrode layer sandwiched between the first insulating layer and the second insulating layer; and

    a buried strap out-diffusion region formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.

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