Power semiconductor devices and methods of manufacture

• US 20050167742A1
• Filed: 12/29/2004
• Published: 08/04/2005
• Est. Priority Date: 01/30/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yun, Chongman, Jang, H.C., Rexer, Christopher L., Jung, J.Y., Challa, Ashok, Herrick, Robert, Probst, Dean E., Murphy, James J., Losee, Becky, Elbanhawy, Alan, Wang, Qi, Wilson, Peter H., Yedinak, Joseph A., Stokes, Richard, Marchant, Bruce D., Dolny, Gary M., Selsley, Adam, Sapp, Steven P., Kraft, Nathan L., Sani, Babak S., Kocon, Christopher B., Grebs, Thomas E., Ridley, Rodney S., Woolsey, Debra S., Madson, Gordon K., Lee, J.G., Mytych, John
• Granted Patent: US 7,345,342 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Claims

1. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench; and

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region.

2. The semiconductor device of claim 1 wherein the charge control trench is lined with a layer of dielectric material and substantially filled with conducive material.

3. The semiconductor device of claim 2 wherein a source electrode electrically couples the conductive material inside the charge control trench to the source region.

4. The semiconductor device of claim 1 wherein inside the charge control trench is disposed a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material.

5. The semiconductor device of claim 4 wherein the plurality of conductive layers inside the charge control trench are electrically biased to provide vertical charge balancing in the drift region.

6. The semiconductor device of claim 5 wherein the plurality of conductive layers inside the charge control trench are configured to be independently biased.

7. The semiconductor device of claim 4 wherein thicknesses of the plurality of conductive layers inside the charge control trench vary.

8. The semiconductor device of claim 1 wherein the thickness of a first conductive layer deeper inside the charge control trench is smaller than the thickness of a second conductive layer that is disposed above the first conductive layer.

9. The semiconductor device of claim 1 wherein the first conductive layer inside the active trench forms a first shield electrode configured to be electrically biased to a desired potential.

10. The semiconductor device of claim 1 wherein the first shield electrode and the source regions are configured to be electrically coupled to substantially the same potential.

11. The semiconductor device of claim 1 wherein the active trench further comprises a second shield electrode made of conductive material disposed below the first shield electrode.

12. The semiconductor device of claim 11 wherein the first and second shield electrodes vary in thickness.

13. The semiconductor device of claim 11 wherein the first and second shield electrodes are configured to be independently biased.

14. The semiconductor device of claim 1 wherein the charge control trench is substantially filed with dielectric material.

15. The semiconductor device of claim 14 further comprising a lining of second conductivity material extending along exterior sidewalls of the charge control trench.

16. The semiconductor device of claim 1 further comprising a Schottcky structure formed between the charge control trench and a second adjacent charge control trench.

17. The semiconductor device of claim 1 wherein the first conductive layer inside the active trench forms a secondary gate electrode that is configured to be electrically biased to a desired potential.

18. The semiconductor device of claim 17 wherein the gate electrode and the secondary gate electrode are configured to be independently electrically biased.

19. The semiconductor device of claim 18 wherein the secondary gate electrode is configured to be biased at a constant potential at approximately the threshold voltage of the semiconductor device.

20. The semiconductor device of claim 18 wherein the secondary gate electrode is configured to be biased at a potential that is greater than a potential applied to the source regions.

21. The semiconductor device of claim 18 wherein the secondary gate electrode is configured to be coupled to a potential at approximately the threshold voltage of the semiconductor device before a switching event.

22. The semiconductor device of claim 17 wherein the charge control trench is lined with a layer of dielectric material and substantially filled with conductive material.

23. The semiconductor device of claim 22 wherein a source electrode is configured to couple the conductive material inside the charge control trench to the source region.

24. The semiconductor device of claim 17 wherein inside the charge control trench is disposed a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material.

25. The semiconductor device of claim 24 wherein the plurality of conductive layers inside the charge control trench are configured to be electrically biased to provide vertical charge balancing in the substrate.

26. The semiconductor device of claim 25 wherein the plurality of conductive layers inside the charge control trench are configured to be independently biased.

27. The semiconductor device of claim 24 wherein sizes of the plurality of conductive layers inside the charge control trench vary.

28. The semiconductor device of claim 27 wherein the size of a first conductive layer deeper inside the charge control trench is smaller than the size of a second conductive layer that is disposed above the first conductive layer.

29. The semiconductor device of claim 17 wherein the charge control trench is substantially filed with dielectric material.

30. The semiconductor device of claim 29 further comprising a lining of second conductivity material extending along exterior sidewalls of the charge control trench.

31. The semiconductor device of claim 17 further comprising a Schottcky structure formed between the charge control trench and a second adjacent charge control trench.

32. The semiconductor device of claim 17 wherein the active trench further comprises a third conductive layer disposed under the secondary gate electrode, the third conductive layer being isolated from the secondary gate electrode and the trench sidewalls and bottom by dielectric material, the third conductive layer forming a shield electrode that is configured to be electrically biased to a desired potential.

33-235. -235. (canceled)