Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same

• US 20050167751A1
• Filed: 11/23/2004
• Published: 08/04/2005
• Est. Priority Date: 02/02/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakajima, Hiroomi, Inoh, Kazumi
• Granted Patent: US 7,301,195 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a semiconductor layer of a first conductive type isolated from said substrate by an insulator layer;

a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in said semiconductor layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body;

an impurity-diffused region of said first conductive type formed at a location in contact with the upper surface of said drain region, said impurity-diffused region having a higher impurity concentration of said first conductive type than an impurity concentration of said second conductive type in said drain region; and

a write transistor including a bipolar transistor having said impurity-diffused region as an emitter region, said drain region as a base region and said channel body as a collector region, said write transistor operative to write data in said memory transistor.

2. The semiconductor memory device according claim 1, wherein said impurity-diffused region is formed in said drain region shallower than said drain region.

3. The semiconductor memory device according claim 2, further comprising an emitter plug connected to said drain region and containing polysilicon of said first conductive type,

wherein said impurity-diffused region is formed to contain an impurity of said first conductive type diffused from inside said emitter plug to said drain region.

4. The semiconductor memory device according claim 1, wherein said impurity-diffused region is connected to said drain region and formed in a conductive emitter plug having a single crystalline structure.

5. The semiconductor memory device according claim 1, further comprising:

a conductive source plug connected to said source region;

a conductive emitter plug connected to said impurity-diffused region; and

a conductive drain plug connected to said drain region, wherein said source plug, said gate electrode, said emitter plug and said drain plug are aligned in this order.

6. The semiconductor memory device according claim 5, wherein a set of said memory transistor and said write transistor configures a memory cell, and wherein in adjacent memory cells, said source plug, said gate electrode, said emitter plug and said drain plug in one of said memory cells, and said drain plug, said emitter plug, said gate electrode and said source plug in the other of said memory cells are aligned in this order.

7. The semiconductor memory device according claim 6, wherein said adjacent memory cells share said drain plug.

8. The semiconductor memory device according claim 1, further comprising:

an interlayer insulator film formed to cover said memory transistor and said write transistor; and

a conductive drain plug buried in said interlayer insulator film and connected to said drain region, wherein said drain plug is projected through said interlayer insulator film and buried in said drain region so as to reach said insulator layer.

9. The semiconductor memory device according claim 1, wherein at least part of said gate electrode is buried in said semiconductor layer.

10. The semiconductor memory device according claim 1, wherein said impurity-diffused region has an impurity concentration of said first conductive type ranging from 1×

10²⁰/cm³ to 1×

10²¹/cm³.

11. The semiconductor memory device according claim 6, comprising:

a cell array including a plurality of said memory cells arranged in matrix; and

a transistor formed in said semiconductor layer and operative to serve as a component in a peripheral circuit of said cell array.

12. The semiconductor memory device according claim 1, wherein said memory transistor stores either a first data state in which said channel body holds excess majority carriers or a second data state in which said channel body holds less majority carriers than said first data state.

13. A semiconductor memory device, comprising:

a substrate;

a semiconductor layer of a first conductive type isolated from said substrate by an insulator layer;

a plurality of memory transistors, each having

a gate electrode,

a pair of impurity regions of a second conductive type formed in said semiconductor layer, and

a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body;

an interlayer insulator film formed to cover said plurality of memory transistors; and

a conductive plug shared by memory transistors in which one of said pair of impurity regions being adjacent each other among said plurality of memory transistors, formed in and projected through said interlayer insulator film, and buried in one of said pair of impurity regions.

14. The semiconductor memory device according claim 13, wherein said plug reaches said insulator layer.

15. The semiconductor memory device according claim 13, wherein said plug contains polysilicon of said second conductive type.

16. A method of manufacturing a semiconductor memory device, comprising:

forming a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in a semiconductor layer of a first conductive type isolated from a substrate by an insulator layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions;

forming an interlayer insulator film to cover said memory transistor;

forming an emitter contact hole in said interlayer insulator film to expose said drain region;

forming an emitter plug of said first conductive type in said emitter contact hole; and

forming an emitter region of said first conductive type in the upper surface of said drain region by thermally diffusing an impurity of said first conductive type from inside said emitter plug to the upper surface of said drain region, said emitter region having a higher impurity concentration of said first conductive type than an impurity concentration of said second conductive type in said drain region.

17. The method according to claim 16, further comprising:

forming in said interlayer insulator film a drain contact hole to expose said drain region and a source contact hole to expose said source region; and

forming a conductive drain plug in said drain contact hole and a conductive source plug in said source contact hole.

18. The method according to claim 17,

the step of forming said memory transistor including forming said drain region as being shared by adjacent memory transistors,

the step of forming said drain contact hole including forming said drain contact hole as reaching said insulator layer, and

the step of forming said drain plug including forming said drain plug in said drain contact hole as being shared by adjacent memory transistors and as reaching said insulator layer.

19. A method of manufacturing a semiconductor memory device, comprising:

forming a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in a semiconductor layer of a first conductive type isolated from a substrate by an insulator layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions;

forming an interlayer insulator film to cover said memory transistor;

forming an emitter contact hole in said interlayer insulator film to expose said drain region; and

forming a single crystalline layer of said first conductive type serving as an emitter region in said emitter contact hole by selective epitaxial growth.

20. A method of manufacturing a semiconductor memory device, comprising:

forming a plurality of memory transistors, each having a gate electrode, a pair of impurity regions of a second conductive type formed in a semiconductor layer of a first conductive type isolated from a substrate by an insulator layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions, in which adjacent memory transistors share one of said pair of impurity regions;

forming an interlayer insulator film to cover said plurality of memory transistors;

forming a contact hole in said interlayer insulator film as entering inside one of said pair of impurity regions; and

forming a conductive plug in said contact hole as entering inside one of said pair of impurity regions and as being shared by adjacent memory transistors.