Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film and method of manufacturing same

• US 20050167765A1
• Filed: 03/28/2005
• Published: 08/04/2005
• Est. Priority Date: 12/27/2000
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hokazono, Akira
• Application Number:
  US11/090,101
• Publication Number:
  US 20050167765A1
• Time in Patent Office: Days
• US Class Current: 257/408
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.

Claims

1. A semiconductor device, comprising:

a device isolation formed in a trench formed in a surface region of a semiconductor substrate, which defines a semiconductor device region, the device isolation comprising a first isolation formed in the trench from a bottom of the trench to a predetermined depth of the trench and a second isolation formed on the first isolation to cover the first isolation, the first isolation including a seam.

15. A semiconductor device according to claim 1, wherein the device isolation is a shallow trench isolation formed in the trench, and the seam extends from the surface of the first isolation in a depth direction of the trench toward a bottom of the trench substantially at a central portion in a width direction of the trench.

16. A semiconductor device according to claim 15, wherein a transistor having source and drain regions is formed in the device region, and the source and drain regions extend to the device isolation.

17. A semiconductor device according to claim 1, wherein a distance from an open surface of the trench to the predetermined depth to which the first isolation is formed is smaller than a minimum diameter of the trench.

2-14. -14. (canceled)