Structure package

• US 20050167797A1
• Filed: 01/29/2004
• Published: 08/04/2005
• Est. Priority Date: 01/29/2004
• Status: Abandoned Application

• Current Assignee: Advanpack Solutions Pte. Ltd. (APS Investment Pte Ltd.)
• Original Assignee: Advanpack Solutions Pte. Ltd. (APS Investment Pte Ltd.)
• Inventors: Bong, Yin Yen
• Application Number:
  US10/766,971
• Publication Number:
  US 20050167797A1
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Wireless devices use protruding antennas for transmitting and receiving data signals. These protruding antennas govern the size and dimensions of these wireless devices. Perpetual reduction in the size of these wireless devices has resulted in an increasing need and desire to eliminate the protruding antennas. Solutions such as reducing the protruding antenna to a stub or using retractable antennas have limitations. The antenna stub sacrifices performance for size reduction. Additionally, the retractable antennas are usually physically separated from the integrated circuit. Electrical connectors interconnecting the external antenna and the integrated circuit can mechanically fail due to connector flexure. An improved integrated structure package is described according to embodiments of the invention where a plurality of pillar structures is used for inter-coupling and spatially displacing one or more semiconductor chips from a substrate to realise a stacked antenna configuration for space and footprint reduction. The good structural integrity of the plurality of pillars also provides mechanically robust electrical interconnections between circuits and antenna patterns formed on the substrate or in the semiconductor chip. The plurality of pillars can be further arranged for providing faraday shielding to an integrated circuit from electromagnetic interference. Dielectric material is further introduced between pairs of the plurality of pillars for forming capacitors for reducing parasitic capacitance.

Claims

1. A structure package comprising:

a first semiconductor chip having a first integrated circuit;

a substrate having a first electrically conductive pattern formed thereon, the first electrically conductive pattern being an antenna layer; and

a plurality of pillars, at least one of the plurality of pillars extending from the first semiconductor chip to the substrate for structurally intercoupling and spatially interdisplacing the first semiconductor chip and the substrate for forming a first channel therebetween,

wherein at least one of the plurality of pillars is for electrically communicating the first integrated circuit with the first electrically conductive pattern.

2. The structure package as in claim 1, the integrated circuit being a data transceiver circuit in operative communication with the first electrically conductive pattern.

3. The structure package as in claim 2, further comprising:

a second electrically conductive pattern, the first electrically conductive pattern and the second electrically conductive pattern being formed on two outwardly opposing faces of the substrate,

wherein at least one of the plurality of pillars is for electrically communicating the integrated circuit with the second electrically conductive pattern.

4. The structure package as in claim 3, the second electrically conductive pattern being an antenna layer and the integrated circuit being in operative communication with the second electrically conductive pattern.

5. The structure package as in claim 4, the first electrically conductive pattern and the second electrically conductive pattern are for transmitting and receiving data signals.

6. The structure package as in claim 2, further comprising:

at least one inter-connector formed through the substrate and the first electrically conductive pattern, the inter-connector for electrically connecting the second electrically conductive pattern to one of the plurality of pillars to thereby electrically inter-communicate the second electrically conductive pattern with the integrated circuit,

wherein the at least one inter-connector is one of electrically insulated from and in electrical communication with the first electrically conductive pattern.

7. The structure package as in claim 2, the first semiconductor chip and the substrate being arranged in a stacked configuration for forming the first channel between the substrate and the first semiconductor chip.

8. The structure package as in claim 7, the first channel being filled with a filler material.

9. The structure package as in claim 2, a portion of the plurality of pillars being spaced apart along the substrate when being disposed between the substrate and the first semiconductor chip.

10. The structure package as in claim 2, at least one of the plurality of pillars being formed from at least two conductive materials.

11. The structure package as in claim 10, one of the at least two conductive material being solder material.

12. The structure package as in claim 2, at least one pair of the plurality of pillars having dielectric material extending therebetween.

13. The structure package as in claim 12, the dielectric material being one of low-K dielectric material and high-K dielectric material.

14. The structure package as in claim 2, each of at least a portion of the plurality of pillars being formed abutting at least another one of the plurality of pillars along the substrate for enclosing a shielded space between the substrate and the first semiconductor chip, the shielded space for electrically shielding at least one of at least a portion of the first integrated circuit of the first semiconductor chip and at least a portion of the first electrically conductive pattern formed on the substrate.

15. The structure package as in claim 2, the first integrated circuit comprising an antenna.

16. The structure package as in claim 15, the first electrically conductive pattern being at least a portion of a data transceiver circuit.

17. The structure package as in claim 2, further comprising:

a second semiconductor chip having a second integrated circuit, at least one of the plurality of pillars extending from the second semiconductor chip to and spatially displacing the second semiconductor chip from one of the first semiconductor chip and the substrate,

wherein at least one of the plurality of pillars is for electrically communicating the second integrated circuit with at least one of the first integrated circuit and the first electrically conductive pattern.

18. The structure package as in claim 17, the first electrically conductive pattern being at least a portion of a data transceiver circuit and each of the first integrated circuit and the second integrated circuit comprising an antenna.

19. The structure package as in claim 17, the first semiconductor chip, the second semiconductor chip and the substrate being arranged in a stacked configuration with a second channel being formed between the second semiconductor chip and the first semiconductor chip.

20. The structure package as in claim 16, the second channel being filled with a filler material.

21. A data transceiver for transceiving data signals comprising:

a first semiconductor chip having a data transceiver circuit;

a substrate having a first antenna pattern formed thereon; and

a plurality of pillars, at least one of the plurality of pillars extending from the first semiconductor chip to the substrate for structurally intercoupling and spatially interdisplacing the first semiconductor chip and the substrate for forming a first channel therebetween,

wherein at least one of the plurality of pillars is for electrically connecting and operatively communicating the data transceiver circuit with the first antenna pattern.

22. The data transceiver as in claim 21, further comprising:

a second antenna pattern, the antenna pattern and the second antenna pattern being formed on two outwardly opposing faces of the substrate,

wherein at least one of the plurality of pillars is for electrically connecting and operatively communicating the data transceiver circuit with the second antenna pattern.

23. The data transceiver as in claim 22, the first antenna pattern and the second antenna pattern are for transmitting and receiving data signals.

24. The data transceiver as in claim 22, further comprising:

at least one inter-connector formed through the substrate and the first antenna pattern, the inter-connector for electrically connecting the second antenna pattern to one of the plurality of pillars to thereby electrically inter-communicate the second antenna pattern with the data transceiver circuit,

wherein the at least one inter-connector is one of electrically insulated from and in electrical communication with the first antenna pattern.

25. The data transceiver as in claim 22, the first semiconductor chip and the substrate being arranged in a stacked configuration for forming the first channel between the substrate and the first semiconductor chip.

26. A data transceiver for transceiving data signals comprising:

a first semiconductor chip having a first integrated circuit, the first integrated circuit comprising an antenna;

a substrate having a data transceiver circuit formed thereon; and

a plurality of pillars, at least one of the plurality of pillars extending from the first semiconductor chip to the substrate for structurally intercoupling and spatially interdisplacing the first semiconductor chip and the substrate for forming a first channel therebetween,

wherein at least one of the plurality of pillars is for electrically communicating the first integrated circuit with the data transceiver circuit.

27. The data transceiver as in claim 26, each of at least a portion of the plurality of pillars being formed abutting at least another one of the plurality of pillars along the substrate for enclosing a shielded space between the substrate and the first semiconductor chip, the shielded space for electrically shielding at least one of at least a portion of the first integrated circuit of the first semiconductor chip and at least a portion of the data transceiver circuit formed on the substrate.

28. The data transceiver as in claim 27, further comprising:

a second semiconductor chip having a second integrated circuit, the second integrated circuit comprising antenna, at least one of the plurality of pillars extending from the second semiconductor chip to and spatially displacing the second semiconductor chip from the first semiconductor chip,

wherein at least one of the plurality of pillars is for electrically communicating the second integrated circuit with at least one of the first integrated circuit and the first data transceiver circuit.

29. The data transceiver as in claim 28, the first semiconductor chip, the second semiconductor chip and the substrate being arranged in a stacked configuration with a second channel being formed between the second semiconductor chip and the first semiconductor chip.

30. The data transceiver as in claim 27, a portion of the plurality of pillars being spaced apart along the substrate when being disposed between the substrate and the first semiconductor chip.