Enhanced adhesion strength between mold resin and polyimide

• US 20050167807A1
• Filed: 02/17/2005
• Published: 08/04/2005
• Est. Priority Date: 01/28/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Jones, Tsao, Pei-Haw, Chen, Ken, Huang, Chender, Huang, Hank
• Granted Patent: US 7,390,697 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.

Claims

1-10. -10. (canceled)

11. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor surface;

depositing a stress relief interface layer over said semiconductor surface; and

creating at least one opening through said stress relief interface layer.

12. The method of claim 11, said semiconductor surface being a surface of a semiconductor device.

13. The method of claim 11, said stress relief interface layer relieving stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

14. The method of claim 11, wherein said stress relief interface layer comprising polyimide.

15. The method of claim 11, further comprising depositing a layer of mold compound over the surface of said stress relief interface layer, filling said at least one opening created through said stress relief interface layer.

16-19. -19. (canceled)

20. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor surface;

depositing a layer of polyimide over said semiconductor surface; and

creating at least one opening through the layer of polyimide.

21. The method of claim 20, said semiconductor surface being a surface of a semiconductor device.

22. The method of claim 20, wherein said layer of polyimide relieving stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

23. The method of claim 20, further comprising depositing a layer of mold compound over the surface of said layer of polyimide, filling said at least one opening created through said layer of polyimide.

24-31. -31. (canceled)

32. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor surface with a layer of passivation formed thereon;

depositing a stress relief interface layer over said layer of passivation; and

creating at least one opening through said stress relief interface layer.

33. The method of claim 32, said semiconductor surface being a surface of a semiconductor device.

34. The method of claim 32, said stress relief interface layer relieving stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

35. The method of claim 32, wherein said stress relief interface layer comprises polyimide.

36. The method of claim 32, further comprising depositing a layer of mold compound over the surface of said stress relief interface layer, filling said at least one opening created through said stress relief interface layer.

37. A method for applying a stress relief interface layer over a semiconductor surface, comprising the steps of:

providing a semiconductor surface with a layer of passivation formed thereon;

depositing a layer of polyimide over said layer of passivation; and

creating at least one opening through the layer of polyimide.

38. The method of claim 37, said semiconductor surface being a surface of a semiconductor device.

39. The method of claim 37, wherein said layer of polyimide relieves stress introduced by mismatched Coefficients of Thermal Expansion (CTE) of thermally interacting layers.

40. The method of claim 37, further comprising depositing a layer of mold compound over the surface of said layer of polyimide, filling said at least one opening created through said layer of polyimide.