Control circuits and methods including delay times for multi-threshold CMOS devices

• US 20050168242A1
• Filed: 11/23/2004
• Published: 08/04/2005
• Est. Priority Date: 01/29/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Won, Hyo-sig
• Granted Patent: US 7,215,155 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

Multi-Threshold CMOS (MTCMOS) devices include a high threshold voltage current control switch that is responsive to a first control signal, a low threshold voltage logic circuit and a flip-flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal. A control circuit also is provided that is configured to change a logic state of the second control signal and then, after a first delay, to change a logic state of the first control signal, in response to the MTCMOS device entering a sleep mode. The control circuit is further configured to change the logic state of the first control signal and then, after a second delay that is different from the first delay, to change the logic state of the second control signal in response to the MTCMOS device entering an active mode. Related methods also are provided.

Claims

1. A Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) device comprising:

a high threshold voltage current control switch that is responsive to a first control signal;

a low threshold voltage logic circuit;

a flip flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal; and

a control circuit that is configured to change a logic state of the second control signal from a first logic state to a second logic state and, after a predetermined delay time tD1, to change a logic state of the first control signal from the second logic state to the first logic state when the MTCMOS device is converted from an active mode to a sleep mode, and is further configured, when the MTCMOS device is converted from the sleep mode to the active mode, to change the logic state of the first control signal from the first logic state to the second logic state and, after a predetermined delay time tD2 that is different from tD1, to change the logic state of the second control signal from the second logic state to the first logic state.

2. The MTCMOS device of claim 1, wherein the control circuit is further configured to convert the MTCMOS device from the sleep mode into the active mode in response to predetermined wakeup signals EXTWKU and RTCWKU, and to convert the MTCMOS device from the active mode into the sleep mode in response to a predetermined stop signal STOP_ON.

3. The MTCMOS device of claim 1, wherein:

the first control signal turns the current control switch on in the second logic state, and turns the current control switch off in the first logic state; and

the second control signal stores data of the logic circuit via the flip-flop in the second logic state, and disables the flip-flop in the first logic state.

4. The MTCMOS device of claim 2, wherein the control circuit comprises:

a first buffer configured to receive the external stop signal STOP_ON;

a first delay circuit configured to delay a signal output from the first buffer;

a first OR gate configured to receive the first external wakeup signal EXTWKU and the second external signal wakeup signal RTCWKU;

a first inverter configured to receive a signal output from the first OR gate;

a second delay circuit configured to delay a signal output from the first inverter;

a first control signal output block configured to output the first control signal, by performing at least one logic operation on the stop signal STOP_ON and an output signal of the first delay circuit; and

a second control signal output block configured to output the second control signal by performing at least one logic operation on the stop signal and an output signal of the second delay circuit.

5. The MTCMOS device of claim 4, wherein the first delay circuit comprises a single flip-flop, and the second delay circuit comprises a plurality of flip-flops connected in series.

6. The MTCMOS device of claim 4, wherein the first control signal output block comprises:

a first AND gate configured to receive the stop signal and the output signal of the first delay circuit;

a first NAND gate configured to receive output signals of the first AND gate and the first inverter; and

a second OR gate configured to output the first control signal by receiving an output signal of the first NAND gate and two predetermined control signals.

7. The MTCMOS device of claim 4, wherein the second control signal output block comprises:

a second AND gate configured to receive the stop signal and the output signal of the first buffer;

a third AND gate configured to receive output signals of the second AND gate and the second delay circuit; and

a forth AND gate configured to output the second control signal by receiving an output signal of the third AND gate and two predetermined control signals.

8. The MTCMOS device of claim 5, wherein the first control signal output block comprises:

a first AND gate configured to receive the stop signal and the output signal of the first delay circuit;

a first NAND gate configured to receive output signals of the first AND gate and the first inverter; and

a second OR gate configured to output the first control signal by receiving an output signal of the first NAND gate and two predetermined control signals.

9. The MTCMOS device of claim 5, wherein the second control signal output block comprises:

a second AND gate configured to receive the stop signal and the output signal of the first buffer;

a third AND gate configured to receive output signals of the second AND gate and the second delay circuit; and

a forth AND gate configured to output the second control signal by receiving an output signal of the third AND gate and two predetermined control signals.

10. A Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) device comprising:

a high threshold voltage current control switch that is responsive to a first control signal;

a low threshold voltage logic circuit;

a flip flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal;

a control circuit configured to transfer the second control signal from a first logic state to a second logic state, and to transfer the first control signal from the second logic state to the first logic state after a predetermined delay time tD1 when the MTCMOS device is converted into the sleep mode, the control circuit comprising;

a timing control circuit configured to transfer the first control signal from the first logic state to the second logic state and to transfer the second control signal from the second logic state to the first logic state when the MTCMOS is converted into the active mode; and

an initialization control circuit configured to initialize a reset flip-flop, to initialize the first control signal to the second logic state via signals output from the reset flip-flop, and to initialize the second control signal to the first logic state, upon initialization of the MTCMOS device.

11. The MTCMOS device of claim 10, wherein the control circuit is further configured to convert the MTCMOS device from the sleep mode into the active mode in response to predetermined wakeup signals EXTWKU and RTCWKU, and to convert the MTCMOS device from the active mode into the sleep mode in response to a predetermined stop signal STOP_ON.

12. The MTCMOS device of claim 10, wherein:

the first control signal turns the current control switch on in the second logic state and turns the current control switch off in the first logic state; and

the second control signal stores data of the logic circuit via the flip-flop in the second logic state and disables the flip-flop in the first logic state.

13. A MTCMOS device of claim 10:

wherein the low threshold voltage logic circuit is connected between a first power source voltage and a first operational voltage, is configured to perform an operation or function, and includes a MOS transistor with a low voltage level V_th; and

wherein the high threshold voltage current control switch is connected between the first operational voltage and a second power source voltage, is configured to control current flow in response to the first control signal, and includes a high voltage level V_th transistor.

14. A method of controlling an active mode of a Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) device comprising:

producing predetermined wakeup signals EXTWKU and RTCWKU including a pulse in a second logic state having a predetermined width;

transferring a first control signal that controls a current flow of the MTCMOS device to the second logic state in response to the predetermined wakeup signals;

transferring a second control signal that controls a flip-flop block for storing data of a logic circuit block of the MTCMOS device after a predetermined delay time from when the first control signal is transferred to the second logic state; and

transferring a stop signal STOP_ON that converts the MTCMOS device to a sleep mode, to the first logic state.

15. A method of controlling a sleep mode of a Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) device, comprising:

transferring a stop signal STOP_ON that converts the MTCMOS device to a sleep mode;

transferring a second control signal that controls a flip-flop for storing data of a logic circuit block of the MTCMOS device, in response to the stop signal; and

transferring a first control signal that controls a current flow of the MTCMOS device after a predetermined delay from when the second control signal is transferred to the second logic state.

16. A Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) device comprising:

a high threshold voltage current control switch that is responsive to a first control signal;

a low threshold voltage logic circuit;

a flip flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal; and

a control circuit that is configured to change a logic state of the second control signal and then, after a first delay, to change a logic state of the first control signal, in response to the MTCMOS device entering a sleep mode, and further configured to change the logic state of the first control signal and then, after a second delay that is different from the first delay, to change the logic state of the second control signal, in response to the MTCMOS device entering an active mode.

17. The MTCMOS device of claim 16 wherein the second delay is longer than the first delay.

18. The MTCMOS device of claim 16 wherein the control circuit is configured to change the logic state of the second control signal from a first logic state to a second logic state and then, after a first delay, to change a logic state of the first control signal from the second logic state to the first logic state, in response to the MTCMOS device entering a sleep mode, and is further configured to change the logic state of the first control signal from the first logic state to the second logic state and then, after a second delay that is different from the first delay, to change the logic state of the second control signal from the second logic state to the first logic state, in response to the MTCMOS device entering an active mode.

19. A method of controlling a Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) device that comprises a high threshold voltage current control switch that is responsive to a first control signal, a low threshold voltage logic circuit, and a flip flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal, the method comprising:

changing a logic state of the second control signal and then, after a first delay, changing a logic state of the first control signal, in response to the MTCMOS device entering a sleep mode; and

changing the logic state of the first control signal and then, after a second delay that is different from the first delay, changing the logic state of the second control signal, in response to the MTCMOS device entering an active mode.

20. The method of claim 19 wherein the second delay is longer than the first delay.

21. The method of claim 19:

wherein changing a logic state of the second control signal and then, after a first delay, changing a logic state of the first control signal, in response to the MTCMOS device entering a sleep mode comprises changing the logic state of the second control signal from a first logic state to a second logic state and then, after a first delay, changing a logic state of the first control signal from the second logic state to the first logic state, in response to the MTCMOS device entering a sleep mode; and

wherein changing the logic state of the first control signal and then, after a second delay that is different from the first delay, changing the logic state of the second control signal, in response to the MTCMOS device entering an active mode comprises changing the logic state of the first control signal from the first logic state to the second logic state and then, after a second delay that is different from the first delay, changing the logic state of the second control signal from the second logic state to the first logic state, in response to the MTCMOS device entering an active mode.