Multi-threshold MIS integrated circuit device and circuit design method thereof

• US 20050169042A1
• Filed: 04/04/2005
• Published: 08/04/2005
• Est. Priority Date: 11/22/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Miyagi, Satoru
• Granted Patent: US 7,443,224 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Claims

1. A multi-threshold MIS integrated circuit design method, comprising the steps of:

disposing a macro including an internal circuit and a virtual power supply line connected to the internal circuit, the internal circuit including a MIS transistor cell having a first threshold voltage;

disposing a leak-current-shielding MIS transistor cell along a side of a macro frame of the macro, the cell having a second threshold voltage different from the first threshold voltage, the cell having a gate line, the cell having a longitudinal direction coincident with the gate line; and

connecting one and another ends of a current path of the MIS transistor cell to a power supply line and the virtual power supply line, respectively, and connecting the gate line to a power control line.

2. The multi-threshold MIS integrated circuit design method according to claim 1, wherein the first MIS transistor cell has a predetermined size, a plurality of the first MIS transistor cells are disposed along a side of the macro frame of the first macro, and gate lines of each adjacent pair of the first MIS transistor cells are connected to each other.

3. The multi-threshold MIS integrated circuit design method according to claim 1, wherein the macro frame of the first macro is rectangular in shape, and the first MIS transistor cells are disposed along at least two sides of the macro frame.

4. The multi-threshold MIS integrated circuit design method according to claim 1, wherein the first power supply line is connected to a pad formed on the substrate, the pad being for external connection.

5. The multi-threshold MIS integrated circuit design method according to claim 1, wherein the first power supply line has a power supply ring formed in a peripheral of one including the first macro and the first MIS transistor cell.

6. The multi-threshold MIS integrated circuit design method according to claim 1, further comprising the step of:

disposing a second macro, the second macro including a second internal circuit for supplying a control signal to the first power control line, and including the first power supply line connected to both the second internal circuit and a pad formed on the substrate, the pad being for external connection.