Serial type interface circuit, power saving method thereof, and device having serial interface

• US 20050169356A1
• Filed: 10/29/2004
• Published: 08/04/2005
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Takeuchi, Katsuhiko, Sugahara, Hirohide, Myouga, Nobuyuki, Matsubayashi, Sumie, Utsunomiya, Shinichi, Matsumoto, Kazunari
• Granted Patent: US 7,424,628 B2
• Time in Patent Office: Days
• US Class Current: 375/220
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A power saving of a serial interface circuit decreases the unnecessary power consumption of a serial interface circuit, while decreasing the return time and expanding the power saving range. Gates are disposed for stopping the clock supply to a digital portion of the interface circuit while maintaining operation of clock sources in the digital portions. Therefore a quick shift to and return from the power save mode by stopping and restarting clocks is implemented, which further decreases power consumption.

Claims

1. A serial type interface circuit for transmitting/receiving data via a serial interface, comprising:

an analog circuit connected to a serial line for analog-processing transmission/reception signals of the serial line;

a digital circuit connected to said analog circuit for digital-processing the received signals from said analog circuit and the transmission signals to said analog circuit according to clocks;

a clock generation circuit for supplying said clocks to said digital circuit; and

a gate circuit for supplying the clocks of said clock generation circuit to said digital circuit and stopping the supply of the clocks simultaneously with cut of the power of said analog circuit according to a power save instruction.

2. The serial type interface circuit according to claim 1, wherein said analog circuit constitutes a part of a physical layer, and

said digital circuit further comprises;

a first digital circuit constituting the other part of said physical layer; and

a second digital circuit constituting a link layer that performs link control.

3. The serial type interface circuit according to claim 2, wherein said first digital circuit operates with clocks from a first clock source of said analog circuit via a first gate circuit, and

said second digital circuit operates with clocks from a second clock source via a second gate circuit, and controls said first and second gate circuits to be in clock supply stop status according to said power save instruction.

4. The serial type interface circuit according to claim 1, further comprising a clock stop circuit that monitors the reception status in said interface, and controls said gate circuit to be in clock supply stop status when frames are not being received from said interface, according to said power save instruction.

5. The serial type interface circuit according to claim 1, further comprising a clock return circuit that returns said gate circuit to a clock supply status according to a frame transmission request from said interface.

6. The serial type interface circuit according to claim 1, wherein said digital circuit cuts power of said analog circuit and controls said gate circuit to be in clock supply stop status according to the power save instruction received from said interface.

7. The serial type interface circuit according to claim 1, wherein said analog circuit comprises:

a driver to said interface;

a receiver from said interface;

a detection circuit for detecting a burst signal of said interface; and

a clock generation source for generating clocks synchronizing with the signals of said interface,

and wherein said digital circuit returns said gate circuit to the clock supply status according to a frame transmission request that said detection circuit detected from the burst signal.

8. A power save method for an interface circuit for transmitting/receiving data via a serial interface, comprising the steps of:

controlling a gate circuit that supplies and stops clocks of a clock generation circuit to a digital circuit to be in a clock supply stop status according to a power save instruction, in said interface circuit comprising an analog circuit connected to a serial line for analog-processing transmission/reception signals of the serial line, and said digital circuit connected to said analog circuit for digital-processing the received signals from said analog circuit and the transmission signals to said analog circuit according to clocks; and

controlling said gate circuit to be in a clock supply status according to a return instruction.

9. The power save method for an interface circuit according to claim 8, further comprising a step of operating a first digital circuit constituting a part of a physical layer with clocks from a first clock source of an analog circuit constituting the other part of said physical layer via a first gate circuit, and operating a second digital circuit constituting a link layer with clocks of a second clock source via a second gate circuit,

wherein said step of controlling to said supply stop status further comprises a step of controlling said first and second gate circuits to be in said clock supply stop status according to said power save instruction.

10. The power save method for an interface circuit according to claim 8, wherein said stop control step further comprises a step of monitoring the reception status in said interface by hardware, and controlling said gate circuit to be in said clock supply stop status when frames are not being received from said interface, according to said power save instruction.

11. The power save method for an interface circuit according to claim 8, wherein said return control step further comprises a step of returning said gate circuit to the clock supply status according to a frame transmission request from said interface.

12. The power save method for an interface circuit according to claim 8, wherein said stop control step comprises a step of cutting power of said analog circuit and controlling said gate circuit to be in said clock supply stop status according to a power save instruction received from said interface.

13. The power save method for an interface circuit according to claim 8, wherein said return control step comprises a step of returning said gate circuit to the clock supply status according to a frame transmission request detected from a burst signal by a detection circuit of said analog circuit, said analog circuit comprising a driver to said interface, a receiver from said interface, said detection circuit for detecting a burst signal of said interface, and a clock generation source for generating clocks synchronizing with the signals of said interface.

14. A serial interface device for transmitting/receiving data with a host via a serial interface, comprising:

a serial interface circuit; and

a processing circuit connected to said serial interface circuit for transmitting/receiving data with said host,

wherein said serial interface circuit comprises;

an analog circuit connected to a serial line for analog-processing transmission/reception signals of the serial line;

a digital circuit connected to said analog circuit for digital-processing the received signals from said analog circuit and the transmission signals to said analog circuit according to clocks;

a clock generation circuit for supplying said clocks to said digital circuit; and

a gate circuit for supplying the clocks of said clock generation circuit to said digital circuit and stopping the supply of the clocks simultaneously with cut of the power of said analog circuit according to a power save instruction.

15. The serial interface device according to claim 14, wherein said analog circuit constitutes a part of a physical layer, and

said digital circuit comprises:

a first digital circuit constituting the other part of said physical layer; and

a second digital circuit constituting a link layer that performs link control.

16. The serial interface device according to claim 15, wherein said first digital circuit operates with clocks from a first clock source of said analog circuit via a first gate circuit, and

said second digital circuit operates with clocks from a second clock source via a second gate circuit, and controls said first and second gate circuits to be in said clock supply stop status according to said power save instruction.

17. The serial interface device according to claim 14, further comprising a clock stop circuit that monitors the reception status in said interface, and controls said gate circuit to be in said clock supply stop status when frames are not being received from said interface, according to said power save instruction.

18. The serial interface device according to claim 14, further comprising a clock return circuit that returns said gate circuit to the clock supply status according to a frame transmission request from said interface.

19. The serial interface device according to claim 14, wherein said digital circuit cuts power of said analog circuit and controls said gate circuit to be in said clock supply stop status according to the power save instruction received from said interface.

20. The serial interface device according to claim 14, wherein said analog circuit comprises:

a driver to said interface;

a receiver from said interface;

a detection circuit for detecting a burst signal of said interface; and

a clock generation source for generating clocks synchronizing with the signals of said interface,

and wherein said digital circuit returns said gate circuit to the clock supply status according to a frame transmission request that said detection circuit detected from the burst signal.