Signal processor

• US 20050169532A1
• Filed: 09/15/2004
• Published: 08/04/2005
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamana, Akifumi, Yamaguchi, Ryouji
• Granted Patent: US 7,551,227 B2
• Time in Patent Office: Days
• US Class Current: 382/200
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56

Abstract

A signal processor includes a picture input section for receiving a video bit stream, a video decoding section for decoding the video bit stream, a picture display section for outputting decoded data from the video decoding section, a digital image input section for receiving digital image data, a digital image display section for outputting the digital image data, a blending section for generating a picture signal from the digital image display section and the picture display section, an audio input section for receiving the digital audio data and the audio bit stream, an audio decoding section for decoding audio data and the audio bit stream, an audio output section for adding an audio signal to data from the audio decoding section to generate a signal and outputting the generated signal, and a synchronizing section for synchronizing respective outputs of the blending section and the audio output section.

Claims

1. A signal processor comprising:

a digital input section for separately receiving an encoded video bit stream, digital image data, an encoded audio bit stream and digital audio data;

a data buffer capable of holding the encoded video bit stream, the digital image data, the encoded audio bit stream and the digital audio data, each being separately output from the digital input section;

a decoding section including a video decoding section for receiving the encoded video bit stream held in the data buffer and outputting the decoded video bit stream and an audio decoding section for receiving the digital audio data and the encoded audio bit stream and outputting the digital audio data and the decoded audio bit stream; and

a synthesizing section for controlling an operation of the audio decoding section to synchronize an output of the encoded audio bit stream, an output of the digital audio data and a display of the digital image data.

2. The signal processor of claim 1, wherein the synchronizing section delays a start of decoding in the audio decoding section, thereby synchronizing an output of the decoded audio bit stream, the output of the digital audio data and a display of the digital image data.

3. The signal processor of claim 1, further comprising an output section including

a picture display section for receiving the decoded video bit stream and outputting the decoded video bit stream as display data,

a digital image display section for receiving the digital image data held in the data buffer and outputting the digital image data as display data, and

an audio output section for outputting the decoded audio bit stream and the digital audio data,

wherein the synchronizing section synchronizes an output of the digital image display section and an output of the audio output section.

4. The signal processor of claim 3,

wherein the digital input section includes a picture input section for receiving the encoded video bit stream and a digital image input section for receiving the digital image data, and

wherein the synchronizing section includes an input detection section for detecting an input of the digital image data into the digital image input section, a counter section for counting an elapsed time from a time at which the input detection section detects the input of the digital image data, a first input/output total time section for holding a time difference between a first total time, i.e., a required total time from a time at which the digital image data is received by the digital image input section to a time at which the digital image data is output from the digital image display section and a second total time, i.e., a required total time from a time at which the digital audio data is received by the audio decoding section to a time at which the digital audio data is output from the audio output section, and a first comparison section for making, if the time difference between the first and second total times and a count value of the counter section are judged equal to each other, the audio decoding section start decoding of the audio bit stream.

5. The signal processor of claim 4, wherein if an absolute value of a difference between the time difference between the first and second total times and the counter value of the counter section is 1/60 seconds or smaller, the first comparison section makes the audio decoding section start decoding of the audio bit stream.

6. The signal processor of claim 4, wherein the audio decoding section does not output the digital audio data received by the audio input section to the audio output section until decoding is started according to an instruction from the first comparison section.

7. The signal processor of claim 4, wherein the audio input section does not output the digital audio data to the audio output section until the first comparison section gives an instruction for starting decoding.

8. The signal processor of claim 3,

wherein the digital input section includes an audio input section for receiving the audio bit stream and the digital audio data, and

wherein the data buffer includes an audio stream buffer for holding the digital audio data received by the audio input section.

9. The signal processor of claim 3,

wherein the digital input section includes a picture input section for receiving the encoded video bit stream, a digital image input section for receiving the digital image data and an audio input section for receiving the audio bit stream and the digital audio data, and

wherein the synchronizing section includes a system time clock counter for generating a time, a second input/output total time section for holding a third total time, i.e., a processing time from a time at which the encoded video bit stream is received by the picture input section to a time at which the decoded video bit stream is output from the picture display section, and an adding section for giving an instruction for inserting as picture time information a value obtained by adding the third total time output from the second input/output total time section into the time generated by the system clock counter while giving an instruction for inserting as audio time information the value into the digital audio data.

10. The signal processor of claim 9,

wherein the synchronizing section further includes

a VTC detection section for detecting the picture time information of the digital image data from the data buffer,

an ATC detection section for detecting the audio time information of the digital audio data from the data buffer,

a second comparison section for giving the digital image display section an instruction for outputting the digital image data if a difference between an output value of the system time clock counter and the picture time information detected in the VTC detection section is smaller than a threshold while giving the audio decoding section an instruction for outputting the digital audio data if a difference between the output value of the system time clock counter and the audio time information detected in the ATC detection section is smaller than a threshold.

11. The signal processor of claim 10, wherein if the difference between the output value of the system time clock counter and the picture time information detected in the VTC detection section is the threshold or larger, the second comparison section gives the digital image display section an instruction for outputting the digital image data in a previous field or frame.

12. The signal processor of claim 9, wherein the adding section performs insertion of the picture time information in each vertical synchronizing signal interval of the digital image data.

13. The signal processor of claim 9, wherein the adding section performs insertion of the audio time information in each frame interval of the digital audio data.

14. The signal processor of claim 1, further comprising a selector for selecting, if a plurality of types of the digital audio data are received, one of the plurality of types of the digital audio data and inputting the selected data to the digital input section.

15. The signal processor of claim 3, wherein the digital image data output from the digital image display section is synchronized with a vertical synchronizing signal or a horizontal synchronizing signal.

16. The signal processor of claim 1, wherein the digital audio data received by the digital input section before the audio decoding section starts decoding of the encoded audio bit stream is deleted from the data buffer.

17. The signal processor of claim 1, wherein inputting of the digital audio data and the encoded audio bit stream to the data buffer is stopped until decoding of the encoded video bit stream in the video decoding section is completed.

18. A signal processor comprising:

a digital input section for separately receiving an encoded video bit stream, digital image data, an encoded audio bit stream and digital audio data;

a data buffer capable of separately holding the encoded video bit stream, the digital image data, the encoded audio bit stream and the digital audio data, each being separately output from the digital input section;

a decoding section including a video decoding section for receiving the encoded video bit stream held in the data buffer and outputting the decoded video bit stream and an audio decoding section for receiving the encoded audio bit stream and outputting the decoded audio bit stream;

an output section for receiving an output of the decoding section and outputting the decoded audio bit stream, the digital image data, the decoded audio bit stream and the digital audio data; and

a synchronizing section,

wherein the digital input section includes an audio input section for receiving the encoded audio bit stream and the digital audio data,

wherein the data buffer includes an audio stream buffer for holding the encoded audio bit stream and the digital audio data which have been received by the audio input section,

wherein the decoding section includes an audio decoding section for receiving the digital audio data and the encoded audio bit stream and outputting the digital audio data and the encoded audio bit stream, and

wherein the output section includes an audio output section for receiving an output from the audio decoding section and outputting the digital audio data and the encoded audio bit stream.