Data move method and apparatus
First Claim
1. A non-volatile memory system comprising:
- at least one non-volatile memory device, wherein the at least one non-volatile memory device contains a memory array with a plurality of physical row pages arranged in a plurality of erase blocks, wherein each physical row page containing one or more user data sectors and one or more overhead data areas; and
wherein a non-split data move control circuit is adapted to move one or more selected user data sectors and associated overhead data areas stored in one or more physical row pages of a selected source erase block to a target erase block in a modified copy-back move operation such that selected user data sectors and the associated overhead data areas stored in a source physical row page of the source erase block are moved to a target physical row page of the target erase block by reading the selected user data sectors and the associated overhead data areas into an internal latch of the at least one non-volatile memory device, transferring one or more latched user data sectors and associated overhead data areas from the at least one non-volatile memory device, masking the selected user data sectors and the associated overhead data areas, and writing the selected user data sectors and the associated overhead data areas to the target physical row page.
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Accused Products
Abstract
An improved Flash memory device, control circuit, or data handling methods is described that facilitate the moving and consolidating data in split and non-split user/overhead data sector architectures, moving and storing user and overhead data from and to separate non-volatile memory devices, differing erase blocks, or differing sectors of an erase block. This enables ECC checking and masking while moving data. In addition, the use of a split data storage approach is enabled that avoids the issue of potential corruption of both the user data and overhead data due to each being held within close proximity to each other on the same physical row by allowing user/overhead data split across two erase blocks to be easily moved, consolidated, and managed.
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Citations
102 Claims
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1. A non-volatile memory system comprising:
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at least one non-volatile memory device, wherein the at least one non-volatile memory device contains a memory array with a plurality of physical row pages arranged in a plurality of erase blocks, wherein each physical row page containing one or more user data sectors and one or more overhead data areas; and
wherein a non-split data move control circuit is adapted to move one or more selected user data sectors and associated overhead data areas stored in one or more physical row pages of a selected source erase block to a target erase block in a modified copy-back move operation such that selected user data sectors and the associated overhead data areas stored in a source physical row page of the source erase block are moved to a target physical row page of the target erase block by reading the selected user data sectors and the associated overhead data areas into an internal latch of the at least one non-volatile memory device, transferring one or more latched user data sectors and associated overhead data areas from the at least one non-volatile memory device, masking the selected user data sectors and the associated overhead data areas, and writing the selected user data sectors and the associated overhead data areas to the target physical row page. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A non-volatile memory system comprising:
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at least one non-volatile memory device, wherein the at least one non-volatile memory device contains a memory array with a plurality of physical row pages arranged in a plurality of erase blocks, wherein the erase blocks of the at least one non-volatile memory device are arranged in pairs into a plurality of super blocks and each physical row page containing one or more user data sectors and one or more overhead data areas; and
wherein a split data move control circuit is adapted to move one or more selected user data sectors stored in two or more physical row pages of a selected source super block to a target super block such that the selected user data sectors stored in a first source physical row page of the source super block are moved to a first target physical row page of the target super block and the associated overhead data areas of the selected user data sectors stored in a second source physical row page of the source super block are moved to a second target physical row page of the target super block. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A Flash memory system comprising:
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at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more user data sectors and one or more overhead data areas;
wherein the erase blocks of the at least one Flash memory device are arranged in pairs into a plurality of super blocks;
a control circuit adapted to control data accesses to the sectors of the erase block pair of a selected super block such that user data access and overhead data accesses are directed to differing erase blocks of the super block; and
wherein a split data move control circuit is adapted to move one or more selected user data sectors stored in two or more physical row pages of an erase block pair of a selected source super block such that the selected user data sectors stored in a first source physical row page of a first erase block of the source super block are moved to a first target physical row page of a first erase block of a target super block and the associated overhead data areas of the selected user data sectors stored in a second source physical row page of a second erase block of the source super block are moved to a second target physical row page of a second erase block of the target super block. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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25. A non-volatile memory device comprising:
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a memory array containing a plurality of memory cells arranged into a plurality of sectors in a plurality of erase blocks, wherein the erase blocks are arranged in pairs into a plurality of super blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more user data sectors and one or more overhead data areas;
a control circuit, wherein the control circuit is adapted to perform data accesses to the sectors of the erase block pair of a super block such that user data access and overhead data accesses are directed to differing erase blocks of the super block; and
a split data move control circuit, wherein the split data move control circuit is adapted to move one or more selected user data sectors and associated overhead data areas stored in two or more physical row pages of an erase block pair of a selected source super block such that the selected user data sectors stored in a first source physical row page of a first erase block of the source super block are moved to a first target physical row page of a first erase block of a target super block and the associated overhead data areas of the selected user data sectors stored in a second source physical row page of a second erase block of the source super block are moved to a second target physical row page of a second erase block of the target super block. - View Dependent Claims (26, 27, 28)
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29. A non-volatile memory controller comprising:
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a control circuit coupled to a host interface;
a memory device interface for one or more non-volatile memory devices coupled to the memory control circuit, wherein each of the one or more non-volatile memory devices has a memory array containing a plurality of memory cells arranged into a plurality of sectors in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more user data sectors and one or more overhead data areas;
wherein the control circuit is adapted to perform data accesses to the sectors of the plurality of erase blocks of the one or more non-volatile memory devices; and
a non-split data move control circuit, wherein the non-split data move control circuit is adapted to move one or more selected user data sectors and associated overhead data areas stored in one or more physical row pages of a selected source erase block of the one or more non-volatile memory devices such that the selected user data sectors and the associated overhead data areas stored in a source physical row page of the source erase block are moved to a target physical row page of a target erase block by reading the selected user data sectors and the associated overhead data areas into an internal latch of the one or more non-volatile memory devices, transferring one or more latched user data sectors and associated overhead data areas from the at least one non-volatile memory device, masking the selected user data sectors and the associated overhead data areas, and writing the selected user data sectors and the associated overhead data areas to the target physical row page. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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36. A non-volatile memory controller comprising:
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a control circuit coupled to a host interface;
a memory device interface for one or more non-volatile memory devices coupled to the memory control circuit, wherein each of the one or more non-volatile memory devices has a memory array containing a plurality of memory cells arranged into a plurality of sectors in a plurality of erase blocks, wherein the erase blocks are arranged in pairs into a plurality of super blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more user data sectors and one or more overhead data areas;
wherein the control circuit is adapted to perform data accesses to the sectors of the erase block pair of a super block of the one or more non-volatile memory devices such that user data access and overhead data accesses are directed to differing erase blocks of the super block; and
a split data move control circuit, wherein the split data move control circuit is adapted to move one or more selected user data sectors and associated overhead data areas stored in two or more physical row pages of an erase block pair of a selected source super block of the one or more non-volatile memory devices such that the selected user data sectors stored in a first source physical row page of a first erase block of the source super block are moved to a first target physical row page of a first erase block of a target super block and the associated overhead data areas of the selected user data sectors stored in a second source physical row page of a second erase block of the source super block are moved to a second target physical row page of a second erase block of the target super block. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
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44. A non-split data move control circuit comprising:
a control circuit, wherein the control circuit is adapted to receive a non-split user and overhead data move request, command one or more user data sectors and associated overhead data areas of a source physical row page of a source erase block to be read into an internal latch of a non-volatile memory device, command transferring one or more latched user data sectors and associated overhead data areas from the non-volatile memory device, command the masking of the one or more user data sectors and associated overhead data areas in the internal latch, and command writing the one or more user data sectors and associated overhead data areas to a target physical row page of a target erase block.
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45. A split data move control circuit comprising:
a control circuit, wherein the control circuit is adapted to receive a split user and overhead data move request and read one or more user data sectors of a source physical row page of a first erase block of a source erase block pair and write the one or more user data sectors to a target physical row page of a first erase block of a target erase block pair, and read one or more associated overhead data codes from a source physical row page of a second erase block of the source erase block pair and write the one or more associated overhead data codes to a target physical row page of a second erase block of the target erase block pair.
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46. A NAND architecture Flash memory non-split data move control circuit comprising:
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a control circuit coupled to a NAND command circuit, a target row register, a source Pre-Count Counter, a source Post Address Register, and a source Post-Count Counter;
wherein a microprocessor interface, an automation control interface, an external address generation hardware interface, and a NAND Flash interface are coupled to the non-split data move control circuit; and
wherein the non-split data move control circuit is adapted to read one or more user data sectors and/or ECC codes of a source physical row page of a source erase block of a NAND architecture Flash memory device and write the one or more user data sectors and/or ECC codes to a target physical row page of a target erase block addressed by the target row register, where the non-split data move control circuit is adapted to transfer the one or more user data sectors and/or ECC codes from the NAND architecture Flash memory device, and where the non-split data move control circuit is adapted to mask a selected range of read data as it is held in a data latch. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53)
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54. A NAND architecture Flash memory split data move control circuit comprising:
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a control circuit coupled to a NAND command circuit, an A and B target row registers, a source A and B Pre-Count Counters, a source A and B Post Address Register, and a source A and B Post-Count Counters;
wherein a microprocessor interface, an automation control interface, an external address generation hardware interface, and a NAND Flash interface are coupled to the split data move control circuit; and
wherein the split data move control circuit is adapted to read one or more user data sectors and/or ECC codes of a source A physical row page of a first erase block of a source erase block pair and write the one or more user data sectors and/or ECC codes to a target A physical row page of a first erase block of a target erase block pair addressed by the target A row register, and read one or more user data sectors and/or ECC codes from a source B physical row page of a second erase block of the source erase block pair and write the one or more user data sectors and/or ECC codes to a target B physical row page of a second erase block of the target erase block pair addressed by the target B row register. - View Dependent Claims (55, 56, 57, 58, 59, 60, 61, 62)
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63. A method of operating a non-volatile memory system comprising:
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reading data of a physical page row of a source erase block from a selected non-volatile memory device of one or more non-volatile memory devices;
transferring selected data from the selected non-volatile memory device;
masking off a first selected range of data column bit values; and
writing the first selected range of data column bit values to a physical page row of a target erase block. - View Dependent Claims (64, 65, 66, 67, 68)
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69. A method of operating a split data non-volatile memory system comprising:
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reading data of a physical page row of a first source erase block of a source super block from a selected non-volatile memory device of one or more non-volatile memory devices;
masking off a first selected range of data column bit values;
writing the first selected range of data column bit values to a physical page row of a first target erase block of a target super block;
reading data of a physical page row of a second source erase block of the source super block;
masking off a second selected range of data column bit values; and
writing the second selected range of data column bit values to a physical page row of a second target erase block of the target super block. - View Dependent Claims (70, 71, 72, 73, 74)
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75. A method of operating a split data non-volatile memory system comprising:
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reading one or more user data sectors of a physical page row of a first source erase block of a source super block from a selected non-volatile memory device of one or more non-volatile memory devices;
writing the one or more user data sectors to a physical page row of a first target erase block of a target super block;
reading one or more overhead data areas of a physical page row of a second source erase block of the source super block; and
writing the one or more overhead data areas to a physical page row of a second target erase block of a target super block. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82)
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83. A method of moving data in a memory system comprising:
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reading one or more user data sectors and one or more overhead data areas of a physical page row of a source erase block from a selected non-volatile memory device of one or more non-volatile memory devices;
transferring selected data of the one or more user data sectors and one or more overhead data areas from the selected non-volatile memory device;
masking the one or more user data sectors and one or more overhead data areas; and
writing the one or more user data sectors and one or more overhead data areas to a physical page row of a target erase block.
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84. A method of moving split data in a memory system comprising:
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reading one or more user data sectors of a physical page row of a first source erase block of a source super block from a selected non-volatile memory device of one or more non-volatile memory devices;
writing the one or more user data sectors to a physical page row of a first target erase block of a target super block;
reading one or more overhead data areas of a physical page row of a second source erase block of the source super block; and
writing the one or more overhead data areas to a physical page row of a second target erase block of a target super block.
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85. A system comprising:
a host coupled to a Flash memory system, wherein the Flash memory system comprises;
at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more user data sectors and one or more overhead data areas;
a control circuit adapted to control data accesses to the sectors of a selected erase block; and
wherein a non-split data move control circuit is adapted to move one or more selected user data sectors and associated overhead data areas stored in one or more physical row pages of the selected source erase block to a target erase block in a modified copy-back move operation such that selected user data sectors and the associated overhead data areas stored in a source physical row page of the source erase block are moved to a target physical row page of the target erase block by reading the selected user data sectors and the associated overhead data areas into an internal latch of the at least one Flash memory device, transferring one or more latched user data sectors and associated overhead data areas from the at least one Flash memory device, masking the selected user data sectors and the associated overhead data areas, and writing the selected user data sectors and the associated overhead data areas to the target physical row page. - View Dependent Claims (86, 87, 88)
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89. A system comprising:
a host coupled to a Flash memory system, wherein the Flash memory system comprises;
at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more user data sectors and one or more overhead data areas;
wherein the erase blocks of the at least one Flash memory device are arranged in pairs into a plurality of super blocks;
a control circuit adapted to control data accesses to the sectors of the erase block pair of a selected super block such that user data access and overhead data accesses are directed to differing erase blocks of the super block; and
wherein a split data move control circuit is adapted to move one or more selected user data sectors stored in two or more physical row pages of an erase block pair of a selected source super block such that the selected user data sectors stored in a first source physical row page of a first erase block of the source super block are moved to a first target physical row page of a first erase block of a target super block and the associated overhead data areas of the selected user data sectors stored in a second source physical row page of a second erase block of the source super block are moved to a second target physical row page of a second erase block of the target super block. - View Dependent Claims (90, 91, 92)
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93. A method of moving data in a split data NAND architecture Flash memory system comprising:
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reading data of a physical page row of a first source erase block of a source super block from a selected NAND architecture Flash device of one or more non-volatile memory devices into an internal data latch;
writing the data by;
masking off a first selected range of data column bit values in the internal data latch, and writing the first selected range of data column bit values in the internal data latch to a physical page row of a first target erase block of a target super block of the selected NAND architecture Flash memory device;
reading data of a physical page row of a second source erase block of the source super block into the internal data latch; and
writing the data by;
masking off a second selected range of data column bit values in the internal data latch, and writing the second selected range of data column bit values from the internal data latch to a physical page row of a second target erase block of the target super block. - View Dependent Claims (94, 95, 96, 97, 98, 99, 100)
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101. A non-volatile memory system comprising:
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at least one non-volatile memory device, wherein the at least one non-volatile memory device contains a memory array with a plurality of physical row pages arranged in a plurality of erase blocks, wherein each physical row page contains one or more user data sectors and one or more overhead data areas; and
wherein a data move control circuit has a means for moving one or more selected user data sectors and one or more associated overhead areas stored in one or more physical row pages of a selected source erase block to a target erase block such that the selected user data sectors and associated overhead areas are masked and transferred from the at least one non-volatile memory device as they are moved.
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102. A non-volatile memory system comprising:
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at least one non-volatile memory device, wherein the at least one non-volatile memory device contains a memory array with a plurality of physical row pages arranged in a plurality of erase blocks, wherein the erase blocks of the at least one non-volatile memory device are arranged in pairs into a plurality of super blocks and each physical row page containing one or more user data sectors and one or more overhead data areas; and
wherein a split data move control circuit has a means for moving one or more selected user data sectors stored in two or more physical row pages of a selected source super block to a target super block such that the selected user data sectors stored in a first source physical row page of the source super block are moved to a first target physical row page of the target super block and the associated overhead data areas of the selected user data sectors stored in a second source physical row page of the source super block are moved to a second target physical row page of the target super block.
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Specification