Buffer control system and method for a memory system having memory request buffers
First Claim
1. A memory hub controller for controlling access to a system memory, comprising:
- a memory request queue storing at least one memory request received through an input port, the memory request queue being operable to issue from an output port each memory request stored in the memory request queue responsive to a flow control signal;
a response queue coupled to receive through an input port read responses containing each read data and a read status signal identifying read requests corresponding to the read data, the response queue further being coupled to receive through the input port write responses each having a write status signal identifying write requests that have been serviced, the response queue being operable to couple at least the read data from each read response signal to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and
a buffer management unit coupled to receive the read status signals and the write status signals from the response queue, the buffer management unit having a read buffer monitor circuit to determine from the read status signals the number of outstanding read requests issued by the memory request queue and having a write buffer monitor circuit to determine from the write status signals the number of outstanding write requests issued by the memory request queue, the buffer management unit further having a flow control circuit coupled to the read and write buffer monitor circuits to generate a flow control signal provided to the memory request queue controlling the issuance of memory requests to the system memory based on the number of outstanding read and write requests issued by the memory request queue.
8 Assignments
0 Petitions
Accused Products
Abstract
A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory are separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by independently halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively.
167 Citations
81 Claims
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1. A memory hub controller for controlling access to a system memory, comprising:
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a memory request queue storing at least one memory request received through an input port, the memory request queue being operable to issue from an output port each memory request stored in the memory request queue responsive to a flow control signal;
a response queue coupled to receive through an input port read responses containing each read data and a read status signal identifying read requests corresponding to the read data, the response queue further being coupled to receive through the input port write responses each having a write status signal identifying write requests that have been serviced, the response queue being operable to couple at least the read data from each read response signal to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and
a buffer management unit coupled to receive the read status signals and the write status signals from the response queue, the buffer management unit having a read buffer monitor circuit to determine from the read status signals the number of outstanding read requests issued by the memory request queue and having a write buffer monitor circuit to determine from the write status signals the number of outstanding write requests issued by the memory request queue, the buffer management unit further having a flow control circuit coupled to the read and write buffer monitor circuits to generate a flow control signal provided to the memory request queue controlling the issuance of memory requests to the system memory based on the number of outstanding read and write requests issued by the memory request queue. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory controller coupled to a system memory through a memory bus, comprising:
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a memory request queue to receive and store memory requests, the memory request queue issuing read requests and write requests to the system memory in response to a flow control signal;
a response queue coupled to receive a memory request response having a status signal identifying read requests and write requests that have been serviced by the system memory; and
a memory request flow control circuit coupled to the response queue to receive the status signals and having separate read and write request monitor circuits to monitor the number of outstanding read and write requests issued to the system memory, respectively, the memory request flow control circuit coupled to the memory request queue to provide the flow control signal responsive to the number of outstanding read and write requests to control the issuance of read requests and the issuance of write requests to the system memory. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory hub controller for controlling access to a system memory, comprising:
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a memory request queue storing read and write memory requests and being operable to issue to the system memory the read and write memory requests stored in the memory request queue responsive to read and write request flow control signals received at a queue control terminal;
a response queue coupled to receive from the system memory read responses each having a read status signal identifying read requests that have been serviced and to receive write responses each having a write status signal identifying write requests that have been serviced, the response queue being operable to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and
a buffer management unit coupled to the queue control terminal of the memory request queue and further coupled to the flow control port of the response queue, the buffer management unit operable to determine from the read status signals the number of outstanding read requests issued by the memory request queue and to determine from the write status signals the number of outstanding write requests issued by the memory request queue, and in response to the number of outstanding read and write requests, generate flow control signals to control the issuance of read and write requests by the memory request queue to the system memory. - View Dependent Claims (20, 21, 22, 23)
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24. A memory system, comprising:
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a memory bus for transmitting memory requests and responses thereon;
a plurality of memory modules coupled to the memory bus, each of the modules having;
a plurality of memory devices;
a memory hub coupled to the plurality of devices and the memory bus for receiving memory requests and generating signals in response thereto to operate the plurality of memory devices and service read and write requests, the memory hub including a memory write buffer coupled to the memory bus to store write requests, a memory read queue coupled to the memory devices to receive read data from the memory devices and store the read data for coupling to the memory bus, and further including a response generator to generate a read response including a read status signal identifying read requests corresponding to the read data and to generate a write response including a write status signal identifying write requests that have been serviced; and
a memory controller coupled to the memory bus, the memory controller having;
a memory request queue storing at least one memory request and operable to issue from an output port to the memory modules each memory request stored in the memory request queue responsive to a flow control signal;
a response queue coupled to receive the read responses and write responses, the response queue being operable to couple at least the read data from each read response signal to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and
a buffer management unit coupled to receive the read status signals and the write status signals from the response queue, the buffer management unit having a read buffer monitor circuit to determine from the read status signals the number of outstanding read requests issued by the memory request queue and having a write buffer monitor circuit to determine from the write status signals the number of outstanding write requests issued by the memory request queue, the buffer management unit further having a flow control circuit coupled to the read and write buffer monitor circuits to generate a flow control signal provided to the memory request queue controlling the issuance of memory requests to the memory modules based on the number of outstanding read and write requests issued by the memory request queue. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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33. A memory system, comprising:
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a memory bus for transmitting memory requests and responses thereon;
a system memory having a plurality of memory modules coupled to the memory bus, each of the modules having;
a plurality of memory devices;
a memory hub coupled to the plurality of devices and the memory bus for receiving memory requests and generating signals in response thereto to operate the plurality of memory devices and service read and write requests, the memory hub including a memory write buffer coupled to the memory bus to store write requests, a memory read queue coupled to the memory devices to receive read data from the memory devices and store the read data for coupling to the memory bus, and further including a response generator to generate a read response including a read status signal identifying read requests corresponding to the read data and to generate a write response including a write status signal identifying write requests that have been serviced; and
a memory controller coupled to the system memory through the memory bus, the memory controller having;
a memory request queue to receive and store memory requests, the memory request queue issuing read requests and write requests to the system memory in response to a flow control signal;
a response queue coupled to receive a memory request response having a status signal identifying read requests and write requests that have been serviced by the system memory; and
a memory request flow control circuit coupled to the response queue to receive the status signals and having separate read and write request monitor circuits to monitor the number of outstanding read and write requests issued to the system memory, respectively, the memory request flow control circuit coupled to the memory request queue to provide the flow control signal responsive to the number of outstanding read and write requests to control the issuance of read requests and the issuance of write requests to the system memory. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a controller coupled to a system memory port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory system, comprising;
a memory bus for transmitting memory requests and responses thereon;
a plurality of memory modules coupled to the memory bus, each of the modules having;
a plurality of memory devices;
a memory hub coupled to the plurality of devices and the memory bus for receiving memory requests and generating signals in response thereto to operate the plurality of memory devices and service read and write requests, the memory hub including a memory write buffer coupled to the memory bus to store write requests, a memory read queue coupled to the memory devices to receive read data from the memory devices and store the read data for coupling to the memory bus, and further including a response generator to generate a read response including a read status signal identifying read requests corresponding to the read data and to generate a write response including a write status signal identifying write requests that have been serviced; and
a memory controller coupled to the memory bus, the memory controller having;
a memory request queue storing at least one memory request and operable to issue from an output port to the memory modules each memory request stored in the memory request queue responsive to a flow control signal;
a response queue coupled to receive the read responses and write responses, the response queue being operable to couple at least the read data from each read response signal to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and
a buffer management unit coupled to receive the read status signals and the write status signals from the response queue, the buffer management unit having a read buffer monitor circuit to determine from the read status signals the number of outstanding read requests issued by the memory request queue and having a write buffer monitor circuit to determine from the write status signals the number of outstanding write requests issued by the memory request queue, the buffer management unit further having a flow control circuit coupled to the read and write buffer monitor circuits to generate a flow control signal provided to the memory request queue controlling the issuance of memory requests to the memory modules based on the number of outstanding read and write requests issued by the memory request queue. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
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51. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a controller coupled to a system memory port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory system, comprising;
a memory bus for transmitting memory requests and responses thereon;
a system memory having a plurality of memory modules coupled to the memory bus, each of the modules having;
a plurality of memory devices;
a memory hub coupled to the plurality of devices and the memory bus for receiving memory requests and generating signals in response thereto to operate the plurality of memory devices and service read and write requests, the memory hub including a memory write buffer coupled to the memory bus to store write requests, a memory read queue coupled to the memory devices to receive read data from the memory devices and store the read data for coupling to the memory bus, and further including a response generator to generate a read response including a read status signal identifying read requests corresponding to the read data and to generate a write response including a write status signal identifying write requests that have been serviced; and
a memory controller coupled to the system memory through the memory bus, the memory controller having;
a memory request queue to receive and store memory requests, the memory request queue issuing read requests and write requests to the system memory in response to a flow control signal;
a response queue coupled to receive a memory request response having a status signal identifying read requests and write requests that have been serviced by the system memory; and
a memory request flow control circuit coupled to the response queue to receive the status signals and having separate read and write request monitor circuits to monitor the number of outstanding read and write requests issued to the system memory, respectively, the memory request flow control circuit coupled to the memory request queue to provide the flow control signal responsive to the number of outstanding read and write requests to control the issuance of read requests and the issuance of write requests to the system memory. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59)
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60. A method for managing the issuance of read and write requests to a system memory, comprising:
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separately monitoring the number of outstanding read requests and write requests issued to the system memory;
separately controlling further issuance of read and write requests to the system memory based on the number of outstanding read and write requests, respectively. - View Dependent Claims (61, 62, 63, 64, 65, 66)
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67. A method for managing the issuance of read and write requests to a system memory, comprising:
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monitoring the number of outstanding read requests and write requests issued to the system memory; and
independently halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively. - View Dependent Claims (68, 69, 70, 71, 72, 73)
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74. A method for managing the issuance of read and write requests to a system memory, comprising:
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monitoring the number of outstanding read requests issued to the system memory;
halting the issuance of read requests to the system memory in response to the number of outstanding read requests exceeding a read request threshold;
resuming the issuance of read requests to the system memory in response to the number of outstanding read requests decreasing to less than a read resume threshold;
monitoring the number of outstanding write requests issued to the system memory;
halting the issuance of write requests to the system memory in response to the number of outstanding write requests exceeding a write request threshold; and
resuming the issuance of write requests to the system memory in response to the number of outstanding write requests decreasing to less than a write resume threshold. - View Dependent Claims (75, 76, 77, 78, 79, 80, 81)
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Specification