Intelligent memory device with ASCII registers
First Claim
1. A computing system comprising:
- one or more processing elements;
a memory having a first interface for connecting to a host processor and a second interface, the memory being divided into a plurality of logical partitions, each partition having a range of memory addresses, at least one partition having information describing a particular task, the information including contents of task state register and one or more task data registers, each task data register having an ASCII name; and
a multi-task controller (MTC) that includes a scheduler unit, a dataflow unit, an executive unit, and a resource manager unit, wherein each unit is separately coupled to each of the other units, wherein the dataflow unit is configured to transfer data between the second interface of the memory and one of either the scheduler unit, the executive unit, or resource manager unit, wherein the dataflow unit is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task, wherein the scheduler unit is coupled to the second interface of the memory and to the processing elements, the dataflow unit is coupled to the second interface of the memory, and the resource manager unit is coupled to the one or more processing elements, wherein the resource manager unit is configured to find an available processing element for carrying out a function of a task and to assign a processing element to a current task by providing a linkage between said available processing element and the task, wherein the scheduler unit is configured to select a task as the current task, to obtain the state of the current task via said dataflow unit, and select an assigned processing element to carry out a function of the current task, wherein the executive unit is configured to decode ASCII-encoded instructions relating to a task and request the resource manager unit to set up a processing element to carry out a function of a task; and
wherein the number of processing elements and number of tasks are independent of each other.
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Abstract
An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character ‘A.’ A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.
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Citations
32 Claims
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1. A computing system comprising:
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one or more processing elements;
a memory having a first interface for connecting to a host processor and a second interface, the memory being divided into a plurality of logical partitions, each partition having a range of memory addresses, at least one partition having information describing a particular task, the information including contents of task state register and one or more task data registers, each task data register having an ASCII name; and
a multi-task controller (MTC) that includes a scheduler unit, a dataflow unit, an executive unit, and a resource manager unit, wherein each unit is separately coupled to each of the other units, wherein the dataflow unit is configured to transfer data between the second interface of the memory and one of either the scheduler unit, the executive unit, or resource manager unit, wherein the dataflow unit is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task, wherein the scheduler unit is coupled to the second interface of the memory and to the processing elements, the dataflow unit is coupled to the second interface of the memory, and the resource manager unit is coupled to the one or more processing elements, wherein the resource manager unit is configured to find an available processing element for carrying out a function of a task and to assign a processing element to a current task by providing a linkage between said available processing element and the task, wherein the scheduler unit is configured to select a task as the current task, to obtain the state of the current task via said dataflow unit, and select an assigned processing element to carry out a function of the current task, wherein the executive unit is configured to decode ASCII-encoded instructions relating to a task and request the resource manager unit to set up a processing element to carry out a function of a task; and
wherein the number of processing elements and number of tasks are independent of each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method of processing one or more tasks using one or more processing elements coupled to a multi-task controller, the multi-task controller being coupled to a memory at a first interface and a host processor being coupled to the memory at a second interface, the method comprising:
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selecting, from the memory via the first interface, a next task for execution, the task having a stored state and a sequence of ASCII-encoded task instructions;
obtaining the stored state for the selected task;
for a task in a ‘
Ready_to_execute’
state,accessing the next task instruction in the sequence, and if the task instruction is ‘
request_resource’
instruction, generating appropriate signals, setting the task state to ‘
Wait_for_resource’
, and proceeding to the step of selecting a next task,if the task instruction is a ‘
perform_processing’
instruction, loading the relevant task data into the processing element, activating the processing element, linking the processing element to the task, setting the task state to ‘
Wait_for_response’
, and proceeding to the step of selecting a next task,if the task instruction is a ‘
transfer_result’
instruction, unloading the result from the processing element, copying to the relevant task data register, and setting the task state to ‘
Ready_to_execute’
,if the task instruction is a ‘
signal_host’
instruction, generating the appropriate signal to the host, setting the task state to ‘
Suspend’
, and proceeding to the step of selecting a next task,if the ASCII-encoded task instruction specifies a non-processing operation to be performed, performing the specified non-processing function, and setting the task state to ‘
Ready_to_execute’
;
for a task in the ‘
Wait_for_resource’
state, waiting until a processing element is available to perform a function of the selected task and setting the task state to ‘
Ready_to_execute;
’for a task in the ‘
Wait_for_response’
state, determining whether or not a response is available from the linked processing element, and setting the task state to ‘
Ready_to_execute,’ and
if a response is not available, setting the task state to ‘
Wait or response’
; and
for a task in a ‘
Suspend’
state, waiting for the host processor to set the task state to ‘
Ready_to_execute’
, after the host processor appropriately accesses the memory via the second interface.
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Specification