Array-type computer processor

• US 20050172103A1
• Filed: 02/03/2005
• Published: 08/04/2005
• Est. Priority Date: 02/03/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Fujii, Taro, Kajihara, Nobuki, Inuo, Takeshi, Motomura, Masato, Anjo, Kenichiro, Kami, Hirokazu, Toi, Takao, Awashima, Tooru, Furuta, Kouichiro
• Granted Patent: US 7,650,484 B2
• Time in Patent Office: Days
• US Class Current: 712/10
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

An array-type computer processor obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes are complete, the subsequent instruction codes are data obtained, so that the operation according to a computer program can be performed even if the data volume of the computer program is over the storage capacity.

Claims

1. An array-type computer processor including a data-path unit and a state control unit,

said data-path unit including a plurality of processor elements and a plurality of switch elements, which are arranged in a matrix,

said processor element performing each of data processes according to an instruction code which describes the data in a computer program for each of a plurality of operation states which are sequentially transferred,

said switch element switching and controlling each of connections between a plurality of said processor elements according to said instruction code, and

said state control unit sequentially transferring a context of said instruction code for each of said operation states of said data-path unit, for each of said operation states according to said instruction code and a properly inputted event data, wherein

said array-type computer processor further comprises code-obtaining means for obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with cooperative partial instruction codes of said contexts, from an external program memory which stores data of said computer program,

said state control unit operates with temporarily holding only a predetermined number of instruction codes of said operation states whose data are obtained, and said data-path unit operates with temporarily holding only a predetermined number of instruction codes of said contexts whose data are obtained, and

every time said state control unit and said data-path unit complete their operations with said temporarily-held instruction codes, said code-obtaining means obtains data of said instruction codes of subsequent said operation states and said contexts.

2. An array-type computer processor according to claim 1, wherein

said state control unit detects said operation completion or initial state, and outputs event data for impossible continuation to said code-obtaining means,

said code-obtaining means comprises:

event-input means for receiving an input of said event data for impossible continuation;

state-obtaining means for obtaining data of said operation state at current from said state control unit and obtaining said event data assigning said operation state at a next-stage from said data-path unit, upon input of said event data for impossible continuation;

operation-obtaining means for obtaining data of a predetermined number of instruction codes of subsequent said operation states, from said program memory, according to said operation state whose data are obtained and said inputted event data;

context-detection means for detecting data of a predetermined number of said contexts corresponding to the operation states of said data-obtained instruction codes;

context-obtaining means for obtaining data of the instruction codes of said data-detected contexts, from said program memory;

code-setting means for setting data of said instruction codes of said operation states and said contexts whose data are obtained in said state control unit and said data-path unit; and

event-output means for outputting event data for starting the operation to said state control unit, upon completion of setting data of said instruction codes, and wherein

said state control unit starts to sequentially transfer said operation states, upon input of said event data for starting the operation.

3. An array-type computer processor according to claim 2, wherein

said code-obtaining means further comprises:

relation-generation means for data generating correspondence relations between said contexts which are data detected by said context-detection circuit and said operation states; and

relation-setting means for also setting data of said data-generated correspondence relations in said state control unit, and wherein

said state control unit sequentially transfers said contexts of said data-path unit for each of said operation states which are sequentially transferred according to said data-set correspondence relations.

4. An array-type computer processor according to claim 3, wherein

said code-obtaining means further comprises:

duplication-detection means for detecting duplication between a plurality of last-time contexts and a plurality of this-time contexts; and

update-control means for eliminating obtaining and setting data of the instruction codes of said contexts whose duplication is detected in said data-path unit, from said program memory.

5. An array-type computer processor according to claim 3, wherein

said code-obtaining means further comprises:

update-storage means for data registering various update techniques of said contexts and their update cost;

technique-detection means for detecting data of an update technique which minimizes a total of said update cost from a combination of a plurality of last-time contexts and a plurality of this-time contexts; and

update-control means for allowing the contexts of data-path unit to be data updated with an update technique that is data detected.

6. An array-type computer processor according to claim 5, wherein

said update-control means includes said update technique, which is data registered in said update-storage means and data detected by said technique-detection means, in which said context-obtaining means obtains data of only different instruction codes between said last-time and this-time contexts, and said code-setting means sets data of only a difference between said this-time and last-time instruction codes.

7. An array-type computer processor according to claim 6, wherein

if there are a plurality of different instruction codes between said last-time and this-time contexts, said update-control means selects a combination which minimizes a total of said update cost of said difference.

8. An array-type computer processor according to claim 5, wherein

said data-path unit comprises:

context-storage means for temporarily holding for a predetermined number of said contexts said instruction codes; and

code-initializing means for initializing at a time for said contexts said temporarily-held instruction codes, wherein

said update-control means includes said update technique, in which data are registered in said update-storage means and in which data are detected by said technique-detection means, in which in a predetermined combination of said last-time and this-time contexts, said code-initializing means initializes said last-time context, and then said code-setting means sets data of said this-time context.

9. An array-type computer processor according to claim 5, wherein

said data-path unit comprises:

context-storage means for temporarily holding for a predetermined number of said contexts said instruction codes; and

code-overwriting means for overwriting at a time, on instruction codes of any of said contexts, instruction codes of any of said contexts which are temporarily held in said context-storage means, wherein

said update-control means includes said update technique, which is data registered in said update-storage means and data detected by said technique-detection means, in which in a predetermined combination of a plurality of said last-time and this-time contexts, said code-overwriting means overwrites corresponding said last-time contexts with other said last-time contexts, and then said context-obtaining means obtains data of only said instruction codes different from those of said this-time context, and said code-setting means sets data of said different instruction codes.

10. An array-type computer processor according to claim 2, wherein

said program memory stores a plurality of said computer programs,

said state control unit includes condition-storage means for temporarily holding for each of a plurality of said operation states said instruction codes,

said data-path unit includes context-storage means for temporarily holding for each of a plurality of said contexts said instruction codes,

said condition-storage means and said context-storage means temporarily hold said instruction codes of corresponding said operation states and said contexts of a plurality of said computer programs, and

when said state control unit and said data-path unit are operating with one of a plurality of said temporarily-held computer programs, said code-obtaining means obtains data of a predetermined number of cooperative partial instruction codes of said operation states of other said computer programs, along with corresponding partial instruction codes of said contexts.

11. An array-type computer processor according to claim 10, further comprising:

operation-stopping means for stopping operations of state control unit and data-path unit upon input of event data for program switching in said event-input means;

stop-obtaining means for obtaining said operation state of said stopped state control unit and said processed data of said stopped data-path unit;

stop-holding means for temporarily holding for each of a plurality of said computer programs said data-obtained operation state and processed data; and

switch-setting means for, upon completion of said temporary hold, data reading from said stop-holding means said operation state and said processed data of other said computer programs, and setting data of said operation state and processed data in said state control unit and said data-path unit, wherein

said event-output means outputs, upon completion of said setting of data of, to said state control unit event data for starting the operation, and

said state control unit starts, upon input of said event data for starting the operation, to sequentially transfer said operation states.

12. An array-type computer processor according to claim 10, further comprising:

priority-detection means for detecting priorities of a plurality of said computer programs of which only portions of said instruction codes are temporarily held by said condition-storage means and said context-storage means; and

code-increasing-and-decreasing means for increasing and decreasing among a plurality of said computer programs according to said priorities a number of said instruction codes of which only portions are temporarily held by said condition-storage means and said context-storage means.

13. An array-type computer processor according to claim 12, wherein

said priority-detection means accumulates a frequency of use as said priority for each of portions of said instruction codes of a plurality of said computer programs which are temporarily held by said condition-storage means and said context-storage means, and

said code-increasing-and-decreasing means preferentially deletes said instruction codes with lower said frequency of use.

14. A data-processing system including a data-processing device and a program memory which are connected to each other, wherein

said data-processing device comprises an array-type computer processor according to claim 1, and

said program memory stores data of said computer programs of the array-type computer processor.

15. A data-processing system including a plurality of data-processing devices connected in parallel which perform each of various data processes according to a computer program and event data,

at least one of a plurality of said data-processing devices including one array-type computer processor and a program memory for storing data of said computer program of the array-type computer processor,

said array-type computer processor including a data-path unit and a state control unit,

said data-path unit including a plurality of processor elements and a plurality of switch elements, which are arranged in a matrix,

said processor element performing each of data processes according to an instruction code which describes the data in said computer program for each of a plurality of operation states which are sequentially transferred,

said switch element switching and controlling each of connections between a plurality of said processor elements according to said instruction code, and

said state control unit sequentially transferring a context of said instruction code for each of said operation states of said data-path unit, for each of said operation states according to said instruction code and properly inputted event data, wherein

at least one of a plurality of said data-processing devices includes code-obtaining means for obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with corresponding partial instruction codes of said contexts, from said program memory,

said state control unit of said array-type computer processor operates with temporarily holding only a predetermined number of instruction codes of said operation states whose data are obtained, and said data-path unit operates with temporarily holding only a predetermined number of data-obtained instruction codes of said contexts,

every time said state control unit and said data-path unit complete their operations with said temporarily-held instruction codes, said code-obtaining means obtains data of said instruction codes of subsequent said operation states and said contexts.

16. A data-processing device which is not said array-type computer processor in the data-processing system according to claim 15, comprising:

code-obtaining means for obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with corresponding partial instruction codes of said contexts, from said program memory.

17. A computer program for the data-processing device according to claim 16, causing said data-processing device to perform processes comprising the step of:

obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with corresponding partial instruction codes of said contexts, from an external program memory which stores data of said computer program.

18. A data-processing system including an array-type computer processor and a program memory for storing data of a computer program of said array-type computer processor, which are connected to each other,

said array-type computer processor including a data-path unit and a state control unit, said data-path unit including a plurality of processor elements and a plurality of switch elements, which are arranged in a matrix, said processor element performing each of data processes according to an instruction code which describes the data in said computer program for each of a plurality of operation states which are sequentially transferred, said switch element switching and controlling each of connections between a plurality of said processor elements according to said instruction code, and said state control unit sequentially transferring a context of said instruction code for each of said operation states of said data-path unit, for each of said operation states according to said instruction code and properly inputted event data, wherein

said data-processing system further comprising code-obtaining means for obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with corresponding partial instruction codes of said contexts, said code-obtaining means connecting to said array-type computer processor, from said program memory, wherein

said state control unit of the array-type computer processor operates with temporarily holding only a predetermined number of data-obtained instruction codes of said operation states, and said data-path unit operates with temporarily holding only a predetermined number of data-obtained instruction codes of said contexts,

every time said state control unit and said data-path unit complete their operations with said temporarily-held instruction codes, said code-obtaining means obtains data of said instruction codes of subsequent said operation states and said contexts.

19. A code-obtaining circuit in the data-processing system according to claim 18,

said code-obtaining circuit obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with corresponding partial instruction codes of said contexts, from said program memory.

20. A code-obtaining circuit according to claim 19 integrated with said program memory.